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1. 发明授权

US08542773B2 Digital RF converter, digital RF modulator and transmitter including the same 有权
标题翻译：数字RF转换器，数字RF调制器和发射机包括相同
公开(公告)号：US08542773B2
公开(公告)日：2013-09-24
申请号：US12968731
申请日：2010-12-15
申请人： Hyun Kyu Yu , Jang Hong Choi , Hyun Ho Boo , Pil Jae Park , Mun Yang Park , Seong Do Kim , Sun Bo Shim , Song Cheol Hong
发明人： Hyun Kyu Yu , Jang Hong Choi , Hyun Ho Boo , Pil Jae Park , Mun Yang Park , Seong Do Kim , Sun Bo Shim , Song Cheol Hong
IPC分类号： H04L27/20 , H03C3/00 , H03M3/00 , H03M1/66
CPC分类号： H03M1/68 , H03M1/687 , H03M1/745 , H03M1/747 , H03M3/50
摘要： A digital RF converter, a digital RF modulator, and a transmitter are provided. The digital RF converter includes a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed, a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed, and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.
摘要翻译：提供数字RF转换器，数字RF调制器和发射器。该数字RF转换器包括一个Δ-Σ调制比特（DSMB）子块，其以第一采样速度在输入信号之间产生对应于最低有效n比特的当前幅度，最低有效位（LSB）子块，以低于第一采样速度的第二采样速度产生对应于输入信号中的中间k位的电流幅度，以及最高有效位（MSB）子块，其产生对应于最高有效m位的当前幅度以第二采样速度输入信号。

2. 发明授权

US09276800B2 Single frequency synthesizer based FDD transceiver 有权
标题翻译：基于单频合成器的FDD收发器
公开(公告)号：US09276800B2
公开(公告)日：2016-03-01
申请号：US13608677
申请日：2012-09-10
申请人： Hyun Ho Boo , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
发明人： Hyun Ho Boo , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
IPC分类号： H04J1/02 , H04L27/38 , H04L27/20 , H04L27/233 , H04L27/36 , H04B1/00
CPC分类号： H04L27/3836 , H04B1/0007 , H04L27/206 , H04L27/2092 , H04L27/2332 , H04L27/362 , H04L27/3854
摘要： The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.
摘要翻译：本发明涉及一种基于单频合成器的FDD收发器。单个频率合成器产生并提供载波频率，使得可以在发送和接收时执行上变频和下变频。因此，可以降低整个系统的面积，功耗和设计复杂性，并且可以提高系统的性能。

3. 发明申请

US20110150125A1 DIGITAL RF CONVERTER, DIGITAL RF MODULATOR AND TRANSMITTER INCLUDING THE SAME 有权
标题翻译：数字射频转换器，数字射频调制器和发射器
公开(公告)号：US20110150125A1
公开(公告)日：2011-06-23
申请号：US12968731
申请日：2010-12-15
申请人： Hyun Kyu YU , Jang Hong Choi , Hyun Ho Boo , Pil Jae Park , Mun Yang Park , Seong Do Kim , Sun Bo Shim , Song Cheol Hong
发明人： Hyun Kyu YU , Jang Hong Choi , Hyun Ho Boo , Pil Jae Park , Mun Yang Park , Seong Do Kim , Sun Bo Shim , Song Cheol Hong
IPC分类号： H04L27/00 , H03M3/02 , H03M1/66
CPC分类号： H03M1/68 , H03M1/687 , H03M1/745 , H03M1/747 , H03M3/50
摘要： There are provided a digital RF converter capable of improving a dynamic range and a signal to noise ratio of a transmitter and a digital RF modulator and a transmitter including the same. The digital RF converter may include: a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed; a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed; and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.
摘要翻译：提供了能够改善发射机和数字RF调制器的动态范围和信噪比的数字RF转换器，以及包括该数字RF转换器的发射机。数字RF转换器可以包括：Δ-Σ调制比特（DSMB）子块，其以第一采样速度在输入信号中产生对应于最低有效n比特的电流幅度; 最低有效位（LSB）子块，其以比第一采样速度低的第二采样速度在输入信号中产生对应于中间k位的电流幅度; 和最高有效位（MSB）子块，其以第二采样速度在输入信号中产生对应于最高有效m位的电流幅度。

4. 发明申请

US20130064148A1 SINGLE FREQUENCY SYNTHESIZER BASED FDD TRANSCEIVER 有权
标题翻译：单频合成器FDD收发器
公开(公告)号：US20130064148A1
公开(公告)日：2013-03-14
申请号：US13608677
申请日：2012-09-10
申请人： Hyun Ho BOO , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
发明人： Hyun Ho BOO , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
IPC分类号： H04J1/02
CPC分类号： H04L27/3836 , H04B1/0007 , H04L27/206 , H04L27/2092 , H04L27/2332 , H04L27/362 , H04L27/3854
摘要： The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.
摘要翻译：本发明涉及一种基于单频合成器的FDD收发器。单个频率合成器产生并提供载波频率，使得可以在发送和接收时执行上变频和下变频。因此，可以降低整个系统的面积，功耗和设计复杂性，并且可以提高系统的性能。

5. 发明申请

US20130063199A1 PROGRAMMABLE COMPLEX MIXER 审中-公开
标题翻译：可编程复合混合器
公开(公告)号：US20130063199A1
公开(公告)日：2013-03-14
申请号：US13615423
申请日：2012-09-13
申请人： Seon-Ho HAN , Hyun Ho Boo , Mun Yang Park , Jang Hong Choi , Hyun Kyu Yu
发明人： Seon-Ho HAN , Hyun Ho Boo , Mun Yang Park , Jang Hong Choi , Hyun Kyu Yu
IPC分类号： G06G7/14
CPC分类号： H03D7/165
摘要： Disclosed is a programmable complex mixer. In accordance with the embodiments of the present invention, it is possible to control an output by programming paths and signs of internal signals in a complex mixer to reduce a processing bandwidth, power consumption, and a chip area in a transceiver, thereby improving performance of a transceiver.
摘要翻译：公开了一种可编程复合混合器。根据本发明的实施例，可以通过在复合混频器中编程内部信号的路径和符号来控制输出，以减少收发器中的处理带宽，功耗和芯片面积，从而提高收发器

6. 发明授权

US08217818B2 Digital RF converter and RF converting method thereof 有权
标题翻译：数字RF转换器及其RF转换方法
公开(公告)号：US08217818B2
公开(公告)日：2012-07-10
申请号：US12902125
申请日：2010-10-11
申请人： Jang Hong Choi , Hyun Ho Boo , Hyun Kyu Yu
发明人： Jang Hong Choi , Hyun Ho Boo , Hyun Kyu Yu
IPC分类号： H03M1/66
CPC分类号： H03M3/504 , H03M3/32
摘要： Provided are a digital radio frequency (RF) converter and an RF converting method thereof. The RF frequency converter includes first and second RF output terminals of a differential form outputting an RF signal; a differential switch selectively connecting first and second nodes into the first and second RF output terminals in response to an oscillating waveform; at least one digital delay device column outputting a plurality of unit bits by sequentially delaying an input bit corresponding to the digital input signal; a front-end processor summing an output of the at least one digital delay device column; a plurality of current sources; and a plurality of first switches corresponding to the plurality of current sources, respectively, and delivering currents of current sources whose number corresponds to the sum value of the front-end processor among the plurality of current sources, to one of the first and second nodes.
摘要翻译：提供一种数字射频（RF）转换器及其RF转换方法。 RF频率转换器包括输出RF信号的差分形式的第一和第二RF输出端; 差分开关响应于振荡波形选择性地将第一和第二节点连接到第一和第二RF输出端子中; 至少一个数字延迟装置列通过顺序地延迟对应于数字输入信号的输入位而输出多个单位位; 前端处理器对所述至少一个数字延迟装置列的输出求和; 多个电流源; 以及分别对应于多个电流源的多个第一开关，并将数量对应于多个电流源中的前端处理器的和值的电流源的电流传送到第一和第二节点之一。

7. 发明授权

US08344772B2 Time-to-digital converter and all digital phase-locked loop including the same 有权
标题翻译：时间到数字转换器和所有数字锁相环包括相同的
公开(公告)号：US08344772B2
公开(公告)日：2013-01-01
申请号：US12956498
申请日：2010-11-30
申请人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , G04F10/005 , H03L7/085 , H03L7/103 , H03L2207/50
摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.
摘要翻译：全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

8. 发明申请

US20110148490A1 TIME-TO-DIGITAL CONVERTER AND ALL DIGITAL PHASE-LOCKED LOOP INCLUDING THE SAME 有权
标题翻译：时数转换器和所有数字相位锁定环路
公开(公告)号：US20110148490A1
公开(公告)日：2011-06-23
申请号：US12956498
申请日：2010-11-30
申请人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H03L7/08 , H03M1/50
CPC分类号： H03L7/095 , G04F10/005 , H03L7/085 , H03L7/103 , H03L2207/50
摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.
摘要翻译：全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出来改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

9. 发明授权

US08471739B2 Digital analog converter and method for calibrating sources thereof 失效
标题翻译：数字模拟转换器及其源的校准方法
公开(公告)号：US08471739B2
公开(公告)日：2013-06-25
申请号：US13312449
申请日：2011-12-06
申请人： Jang Hong Choi , Hyun Kyu Yu
发明人： Jang Hong Choi , Hyun Kyu Yu
IPC分类号： H03M1/10
CPC分类号： H03M1/0653 , H03M1/685 , H03M1/747
摘要： Provided is a digital analog converter that output currents having different magnitudes for a digital input value according to a mapping table. The digital analog converter includes: a plurality of current sources; and a calibration unit configured to sort index values for identifying the plurality of current sources according to current magnitudes of the current sources, couple each two current sources which are symmetrical left and right about the center of the sorted index values, and map the current source pairs into a mapping table.
摘要翻译：提供了一种数字模拟转换器，其根据映射表输出对数字输入值具有不同幅度的电流。数字模拟转换器包括：多个电流源; 以及校准单元，被配置为根据当前源的当前幅度对用于识别多个电流源的索引值进行排序，将关于分选的索引值的中心的左右对称的两个电流源耦合，并且将当前源成对映射表。

10. 发明授权

US06668035B2 Structure of delta-sigma fractional type divider 有权
$Structure of delta-sigma fractional type divider$
标题翻译： delta-sigma分数分频器的结构
公开(公告)号：US06668035B2
公开(公告)日：2003-12-23
申请号：US10179840
申请日：2002-06-24
申请人： Seon Ho Han , Jang Hong Choi , Jae Hong Jang , Hyun Kyu Yu
发明人： Seon Ho Han , Jang Hong Choi , Jae Hong Jang , Hyun Kyu Yu
IPC分类号： H03K2100
CPC分类号： H03M7/3022 , H03L7/1978
摘要： The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.
摘要翻译：本发明涉及一种delta-sigma分数型分频器的结构。分频器结构增加了Δ-Σ调制器的外部输入值和输出值，以调制吞咽计数器的值。因此，本发明可以提供一种Δ-Σ分数分频器，其结构简单，并且可以获得具有宽带频率混合能力的Δ-Σ模式的结构的效果。

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