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1. 发明申请

WO2011060078A1 DATA STATE-DEPENDENT CHANNEL BOOSTING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING IN MEMORY 审中-公开
标题翻译：数据状态相关通道提升降低存储器中的通道到浮动门耦合
公开(公告)号：WO2011060078A1
公开(公告)日：2011-05-19
申请号：PCT/US2010/056248
申请日：2010-11-10
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , SHAH, Grishma
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , SHAH, Grishma
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427
摘要： In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.
摘要翻译：在编程操作中，选择的字线上的所选择的存储元件被编程，同时通过通道增强来禁止所选字线上的未选择的存储元件的编程。为了提供足够但不是过高的升压水平，可以基于未选择的存储元件的数据状态来设定升压量。可以为代表较低阈值电压的较低数据状态提供更大量的升压，因此更易受编程干扰的影响。一个共同的升压方案可以用于多个数据状态的组。可以通过调整用于通道预充电操作的电压的时序和幅度以及施加到字线的通过电压来设置升压量。在一种方法中，可以使用未选择字线上的阶梯式通过电压来调整具有所选数据状态的通道的升压。

2. 发明申请

WO2009146235A4 COMPENSATING NON-VOLATILE STORAGE USING DIFFERENT PASS VOLTAGES DURING PROGRAM- VERIFY AND READ 审中-公开
公开(公告)号：WO2009146235A4
公开(公告)日：2009-12-03
申请号：PCT/US2009/042564
申请日：2009-05-01
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W.
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W.
IPC分类号： G11C16/04 , G11C16/34
摘要： Optimized verify and read pass voltages are obtained to improve read accuracy in a non-volatile storage device. The optimized voltages account for changes in unselected storage element resistance when the storage elements become programmed. This change in resistance is referred to as a front pattern effect. In one approach, the verify pass voltage is higher than the read pass voltage, and a common verify voltage is applied on the source and drain sides of a selected word line. In other approaches, different verify pass voltages are applied on the source and drain sides of the selected word line. An optimization process can include determining a metric for different sets of verify and read pass voltages. The metric can indicate threshold voltage width, read errors or a decoding time or number of iterations of an ECC decoding engine.

3. 发明申请

WO2011025731A1 PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES 审中-公开
标题翻译：使用浮动位线的非易失性存储器的部分速度和全速编程
公开(公告)号：WO2011025731A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/046312
申请日：2010-08-23
申请人： SANDISK CORPORATION , MUI, Man , DONG, Yingda , LE, Binh , DUTTA, Deepanshu
发明人： MUI, Man , DONG, Yingda , LE, Binh , DUTTA, Deepanshu
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： Partial speed (fine) and full speed (coarse) programming are achieved for a non-volatile memory system. During a program operation, in a first time period (tl-t3), bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed (fine programming) and bit lines of storage elements to be programmed at a full speed (coarse programming) are fixed at ground potential. In a second time period (t4-t5), the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain grounded. In a third time period (t5-t8), the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.
摘要翻译：对于非易失性存储器系统，实现了部分速度（精细）和全速（粗略）编程。在编程操作期间，在第一时间段（t1-t3）中，要禁止的存储元件的位线被预充电，而要以部分速度（精细编程）编程的存储元件的位线和位线以全速编程的存储元件（粗略编程）固定在地电位。在第二时间段（t4-t5）中，以部分速度编程的存储元件的位线被驱动得较高，而要被禁止的存储元件的位线被浮置，并且存储元件的位线被编程保持接地。在第三时间段（t5-t8）中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

4. 发明申请

WO2010017013A1 COMPENSATING FOR COUPLING DURING READ OPERATIONS IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中读取操作期间的耦合补偿
公开(公告)号：WO2010017013A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/050974
申请日：2009-07-17
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
IPC分类号： G11C11/56 , G11C16/24
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3418
摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.
摘要翻译：通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压字线。当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据相邻存储元件。

5. 发明申请

WO2011094419A1 MULTIBIT PROGRAMMING METHOD IN A NON-VOLATILE MEMORY ALLOWING A NUMBER OF DATA STATE - FAILS AND DATA RECOVERY METHOD IN CASE OF PROGRAMMING FAIL 审中-公开
标题翻译：非易失性存储器中的多编程方法允许数据状态 - 编程失败情况下的故障和数据恢复方法
公开(公告)号：WO2011094419A1
公开(公告)日：2011-08-04
申请号：PCT/US2011/022736
申请日：2011-01-27
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , YAN, Li
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , YAN, Li
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C16/3418 , G11C29/00 , G11C2211/5621 , G11C2211/5642
摘要： An error detection and data recovery operation for a non-volatile memory system. Even after a programming operation for a set of storage elements is successfully completed, the data of some storage elements may be corrupted. For example, erased state storage element may be disturbed by programming of other storage elements. To allow recovery of data in such situations, associated data latches can be configured to allow the erased state storage elements to be distinguished from other data states once programming is completed. Furthermore, a single read operation can be performed after programming is completed. Logical operations are performed using results from the read operation, and values in the data latches, to identify erased state storage elements which have strayed to another data state. If the number of errors exceeds a threshold, a full recovery operation is initiated in which read operations are performed for the remaining states.
摘要翻译：用于非易失性存储器系统的错误检测和数据恢复操作。即使在一组存储元件的编程操作成功完成之后，一些存储元件的数据也可能被破坏。例如，擦除状态存储元件可能受到其他存储元件的编程的干扰。为了允许在这种情况下恢复数据，相关联的数据锁存器可以被配置为允许擦除状态存储元件与编程完成之后的其它数据状态区分开。此外，可以在编程完成之后执行单个读取操作。使用读取操作的结果和数据锁存器中的值执行逻辑运算，以识别已经偏移到另一数据状态的擦除状态存储元件。如果错误数量超过阈值，则启动完全恢复操作，在其中执行剩余状态的读取操作。

6. 发明申请

WO2010051116A1 PAIR BIT LINE PROGRAMMING TO IMPROVE BOOST VOLTAGE CLAMPING 审中-公开
标题翻译：配对线编程，以提高升压钳位
公开(公告)号：WO2010051116A1
公开(公告)日：2010-05-06
申请号：PCT/US2009/058000
申请日：2009-09-23
申请人： SANDISK CORPORATION , LUTZE, Jeffrey, W. , DUTTA, Deepanshu
发明人： LUTZE, Jeffrey, W. , DUTTA, Deepanshu
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C2211/5621
摘要： A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.
摘要翻译：编程技术通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的编程干扰，这增加了禁止信道的钳位升压电位以避免编程干扰。一个方面将交替的相邻位线对组合成第一和第二组。双编程脉冲被施加到选定的字线。第一组位线在第一脉冲期间被编程，并且第二组位线在第二脉冲期间被编程。然后对所有位线执行验证操作。当特定位线被禁止时，其相邻位线中的至少一个也将被禁止，使得特定位线的通道将被充分提升。另一个方面分别编写每第三个位线。修改的布局允许使用奇偶校验感测电路来感测相邻的位线对。

7. 发明申请

WO2011123279A1 EXTRA DUMMY ERASE PULSES AFTER SHALLOW ERASE -VERIFY TO AVOID SENSING DEEP ERASED THRESHOLD VOLTAGE 审中-公开
标题翻译：经过擦除后，可以除去感应深度电压阈值以外的额外的擦除脉冲
公开(公告)号：WO2011123279A1
公开(公告)日：2011-10-06
申请号：PCT/US2011/029240
申请日：2011-03-21
申请人： SANDISK CORPORATION , OOWADA, Ken , DONG, Yingda , DUTTA, Deepanshu
发明人： OOWADA, Ken , DONG, Yingda , DUTTA, Deepanshu
IPC分类号： G11C11/56 , G11C16/34 , G11C16/14
CPC分类号： G11C11/5635 , G11C16/14 , G11C16/3436
摘要： An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses (1502, 1504, 1506, 1508, 1602, 1604) to a substrate, where each erase pulse is followed by a verify operation (1512, 1514, 1516, 1518, 1608). The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached (Verase-max), at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes (1610). The second phase applies one or more extra erase pulses (1606) which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write -erase endurance, while still achieving the desired deep erase.
摘要翻译：用于非易失性存储器的擦除操作包括第一和第二相。第一阶段将一系列电压脉冲（1502,1504,1506,1508,1602,1604）施加到衬底，其中每个擦除脉冲后跟验证操作（1512,1514,1516,1518,1608）。验证操作使用从最终期望的阈值电压电平偏移的验证电平。擦除脉冲以幅度升高直到达到最大电平（Verase-max），此时应用最大电平的附加擦除脉冲。当验证操作通过时，第一阶段结束（1610）。第二阶段施加一个或多个额外的擦除脉冲（1606），其在第一阶段中的幅度高于最后一个擦除脉冲，并且后面没有验证操作。这避免了在深的负阈值电压电平下执行验证操作的需要，这可能导致电荷捕获，从而减少写入耐久性，同时仍然实现期望的深度擦除。

8. 发明申请

WO2011066234A1 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED NUMBER OF VERIFY OPERATIONS 审中-公开
标题翻译：编程非易失性存储器，具有减少的验证数量
公开(公告)号：WO2011066234A1
公开(公告)日：2011-06-03
申请号：PCT/US2010/057666
申请日：2010-11-22
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , HEMINK, Gerrit, Jan
发明人： DUTTA, Deepanshu , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3454 , G11C11/5628 , G11C16/3459 , G11C2211/5621
摘要： A method and non-volatile storage system are provided in which programming speed is increased by reducing the number of verify operations, while maintaining a narrow threshold voltage distribution. A programming scheme performs a verify operation at an offset level, before a verify level of a target data state is reached, such as to slow down programming. However, it is not necessary to perform verify operations at both the offset and target levels at all times. In a first programming phase, verify operations are performed for a given data state only at the target verify level. In a second programming phase, verify operations are performed for offset and target verify levels. In a third programming phase, verify operations are again performed only at the target verify level. Transitions between phases can be predetermined, based on programming pulse number, or adaptive.
摘要翻译：提供了一种方法和非易失性存储系统，其中通过减少验证操作的数量来增加编程速度，同时保持窄的阈值电压分布。在达到目标数据状态的验证级别之前，编程方案在偏移级别执行验证操作，例如减慢编程。但是，始终不必在偏移量和目标电平两者上执行验证操作。在第一个编程阶段，仅在目标验证级别对给定数据状态执行验证操作。在第二个编程阶段，对偏移和目标验证电平执行验证操作。在第三个编程阶段，仅在目标验证级别再次执行验证操作。相位之间的转换可以根据编程脉冲数或自适应来预先确定。

9. 发明申请

WO2011017378A1 PROGRAMMING MEMORY WITH REDUCED PASS VOLTAGE DISTURB AND FLOATING GATE TO-CONTROL GATE LEAKAGE 审中-公开
标题翻译：具有降低输入电压干扰和浮动门控制门控泄漏的编程存储器
公开(公告)号：WO2011017378A1
公开(公告)日：2011-02-10
申请号：PCT/US2010/044317
申请日：2010-08-03
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , CHIN, Henry
发明人： DUTTA, Deepanshu , CHIN, Henry
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3418 , G11C16/3427
摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn-I neighbor storage element, and applying an optimal pass voltage to WLn-I for each group. Initially, the states of the storage elements on WLn-I are read. A program iteration includes multiple program pulses. A first program pulse (1402) is applied to WLn while a first pass voltage (1425) is applied to WLn-1, a first group (1480, 1482, 1488) of WLn storage elements is selected for programming, and a second group (1484, 1486) of WLn storage elements is inhibited. Next, a second program pulse (1404) is applied to WLn while a second pass voltage (1426) is applied to WLn-I, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states (A, B, C, E).
摘要翻译：通过根据其WLn-I相邻存储元件的状态在分离的组中对所选择的字线WLn上的存储元件进行编程，并且对每个所述WLn-I相邻存储元件的WLn-1施加最佳通过电压，从而在非易失性存储系统中减少编程干扰组。最初，读取WLn-I上的存储元件的状态。程序迭代包括多个程序脉冲。当对WLn-1施加第一通过电压（1425）时，第一编程脉冲（1402）被施加到WLn，WLn存储元件的第一组（1480,1482,1488）被选择用于编程，而第二组（ 1484,1486）的WLn存储元件被禁止。接下来，向WLn施加第二编程脉冲（1404），同时将第二通过电压（1426）施加到WLn-I，选择第二组WLn存储元件进行编程，并且第一组WLn存储元件为抑制。组可以包括一个或多个数据状态（A，B，C，E）。

10. 发明申请

WO2010044993A1 MULTI-PASS PROGRAMMING FOR MEMORY USING WORD LINE COUPLING 审中-公开
标题翻译：使用字线耦合的存储器的多通道编程
公开(公告)号：WO2010044993A1
公开(公告)日：2010-04-22
申请号：PCT/US2009/057984
申请日：2009-09-23
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W.
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W.
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3418 , G11C16/3454 , G11C2211/5621 , G11C2211/5648
摘要： A multiple pass programming scheme is optimized using capacitive coupling in the word line to word line direction during program-verify operations. A different pass voltage is used in different programming passes on an adjacent word line of a selected word line which is being verified. In particular, a lower pass voltage can be used in a first pass than in a second pass. The programming process may involve a word line look ahead or zigzag sequence in which WLn is programmed in a first pass, followed by WLn+ 1 in a first pass, followed by WLn in a second pass, followed by WLn+1 in a second pass. An initial programming pass may be performed before the first pass in which storage elements are programmed to an intermediate state and/or to a highest state.
摘要翻译：在编程验证操作期间，使用字线到字线方向的电容耦合来优化多通道编程方案。在正在验证的所选字线的相邻字线上的不同编程遍中使用不同的通过电压。特别地，可以在第一遍中比在第二遍中使用较低通过电压。编程过程可以包括字线前视或之字形序列，其中WLn在第一遍中编程，其次是第一遍中的WLn + 1，之后是第二遍中的WLn，之后是第二遍中的WLn + 1。可以在其中存储元件被编程到中间状态和/或最高状态的第一遍之前执行初始编程遍。

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