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1. 发明申请

WO2009158350A1 IMPROVED PROGRAMMING ALGORITHM TO REDUCE DISTURB WITH MINIMAL EXTRA TIME PENALTY 审中-公开
标题翻译：改进的编程算法，减少距离最小的额外罚款
公开(公告)号：WO2009158350A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048311
申请日：2009-06-23
申请人： SANDISK CORPORATION , LEE, Dana , DUTTA, Deepanshu , DONG, Yingda
发明人： LEE, Dana , DUTTA, Deepanshu , DONG, Yingda
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
摘要翻译：在多遍编程过程中，非易失性存储器中的编程时间会减少。在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

2. 发明申请

WO2008137687A1 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 审中-公开
标题翻译：使用通道隔离开关来促进非易失性存储
公开(公告)号：WO2008137687A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062432
申请日：2008-05-02
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

3. 发明申请

WO2007143399A3 NAND FLASH VERIFY METHOD WITH DIFFERENT COMPENSATED PASS VOLTAGES 审中-公开
公开(公告)号：WO2007143399A3
公开(公告)日：2007-12-13
申请号：PCT/US2007/069590
申请日：2007-05-23
申请人： SANDISK CORPORATION , MOKHLESI, Nima , DONG, Yingda
发明人： MOKHLESI, Nima , DONG, Yingda
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56
摘要： Errors can occur when reading the threshold voltage of a programmed non- volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating gates, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. To account for the back pattern effect, a first voltage is used during a verify operation for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. The combination of these two techniques provides for more accurate storage and retrieval of data.

4. 发明申请

WO2011081910A1 PROGRAMMING NON-VOLATILE STORAGE WITH FAST BIT DETECTION AND VERIFY SKIP 审中-公开
标题翻译：使用快速检测和验证跳过编程非易失性存储
公开(公告)号：WO2011081910A1
公开(公告)日：2011-07-07
申请号：PCT/US2010/060221
申请日：2010-12-14
申请人： SANDISK CORPORATION , CHEN, Changyuan , LUTZE, Jeffrey , DONG, Yingda , HSU, Hua-ling
发明人： CHEN, Changyuan , LUTZE, Jeffrey , DONG, Yingda , HSU, Hua-ling
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G10L15/26 , G11C2211/5621
摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non¬ volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.
摘要翻译：对一组非易失性存储元件进行编程处理以便存储数据。在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

5. 发明申请

WO2011025731A1 PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES 审中-公开
标题翻译：使用浮动位线的非易失性存储器的部分速度和全速编程
公开(公告)号：WO2011025731A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/046312
申请日：2010-08-23
申请人： SANDISK CORPORATION , MUI, Man , DONG, Yingda , LE, Binh , DUTTA, Deepanshu
发明人： MUI, Man , DONG, Yingda , LE, Binh , DUTTA, Deepanshu
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： Partial speed (fine) and full speed (coarse) programming are achieved for a non-volatile memory system. During a program operation, in a first time period (tl-t3), bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed (fine programming) and bit lines of storage elements to be programmed at a full speed (coarse programming) are fixed at ground potential. In a second time period (t4-t5), the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain grounded. In a third time period (t5-t8), the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.
摘要翻译：对于非易失性存储器系统，实现了部分速度（精细）和全速（粗略）编程。在编程操作期间，在第一时间段（t1-t3）中，要禁止的存储元件的位线被预充电，而要以部分速度（精细编程）编程的存储元件的位线和位线以全速编程的存储元件（粗略编程）固定在地电位。在第二时间段（t4-t5）中，以部分速度编程的存储元件的位线被驱动得较高，而要被禁止的存储元件的位线被浮置，并且存储元件的位线被编程保持接地。在第三时间段（t5-t8）中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

6. 发明申请

WO2010017013A1 COMPENSATING FOR COUPLING DURING READ OPERATIONS IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中读取操作期间的耦合补偿
公开(公告)号：WO2010017013A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/050974
申请日：2009-07-17
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , DONG, Yingda , CHIN, Henry , ISHIGAKI, Toru
IPC分类号： G11C11/56 , G11C16/24
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3418
摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.
摘要翻译：通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压字线。当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据相邻存储元件。

7. 发明申请

WO2008083214A1 PROGRAMMING NON-VOLATILE MEMORY WITH REDUCED PROGRAM DISTURB BY REMOVING PRE-CHARG DEPENDENCY ON WORD LINE DATA 审中-公开
标题翻译：通过在字线数据上删除预先确定的程序来编程减少程序干扰的非易失性存储器
公开(公告)号：WO2008083214A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088931
申请日：2007-12-27
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Dana , HEMINK, Gerrit, Jan
IPC分类号： G11C16/04 , G11C16/12 , G11C11/56
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.
摘要翻译：在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。在预充电期间，对于可能已经经过部分编程的某些存储器单元，在较高电压下提供一个或多个预充电使能信号。

8. 发明申请

WO2008073892A2 REDUCING PROGRAM DISTURB IN NON-VOLATILE STORAGE USING EARLY SOURCE-SIDE BOOSTING 审中-公开
标题翻译：利用早期源头提升减少非易失性存储中的程序干扰
公开(公告)号：WO2008073892A2
公开(公告)日：2008-06-19
申请号：PCT/US2007/086981
申请日：2007-12-10
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W.
发明人： DONG, Yingda , LUTZE, Jeffrey, W.
IPC分类号： G11C16/12 , G11C16/10 , G11C16/04
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： Program disturb is reduced in non-volatile storage by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach, a first boost mode is used when the selected word line is a lower or intermediate word line. In the first boost mode, boosting of the source and drain side channels is initiated concurrently. A second boost mode is used when the selected word line is a higher word line. In the second boost mode, boosting of the source side channel occurs early relative to the boosting of the drain side channel. Either boost mode include an isolation voltage which tends to isolate the source and drain side channels from one another.
摘要翻译：通过提升阵列中的未选NAND串以减少非易失性存储器中的编程干扰，使得选定字线的源极侧上的源侧通道在漏极侧通道之前升压，在所选字线的漏极侧。在一种方法中，当所选字线是较低或中间字线时，使用第一升压模式。在第一升压模式中，同时启动源极和漏极侧通道的升压。当所选字线是较高字线时，使用第二升压模式。在第二升压模式中，相对于漏极侧沟道的升压，源极侧沟道的升压发生得较早。任何一种升压模式都包含一个隔离电压，可以将源极和漏极通道相互隔离。

9. 发明申请

WO2008057927A2 REDUCING PROGRAM DISTURB IN NON-VOLATILE MEMORY USING MULTIPLE BOOSTING MODES 审中-公开
标题翻译：使用多种启动模式减少非易失性存储器中的程序干扰
公开(公告)号：WO2008057927A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/083313
申请日：2007-11-01
申请人： SANDISK CORPORATION , LUTZE, Jeffrey, W. , DONG, Yingda
发明人： LUTZE, Jeffrey, W. , DONG, Yingda
IPC分类号： G11C16/12
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A method for operating a non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self- boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.
摘要翻译：一种用于操作减少程序干扰的非易失性存储系统的方法。在编程非易失性存储时实现多种升压模式。例如，可以使用自我增强，地方自我提升，消除区域自我增强和修改的擦除区域自增强。使用一个或多个切换标准来确定何时切换到不同的升压模式。当存储元件被编程在所选择的NAND串中时，升压模式可用于防止未选择的NAND串中的程序干扰。通过切换升压模式，可以在条件变化时使用最佳升压模式。可以基于各种标准来切换升压模式，例如程序脉冲数，程序脉冲幅度，程序通过次数，所选字线的位置，是否使用粗调或精细编程，存储元件是否达到程序状态和/ 或非易失性存储设备的多个程序周期。

10. 发明申请

WO2011133404A1 PROGRAMMING NON-VOLATILE STORAGE INCLUDNG REDUCING IMPACT FROM OTHER MEMORY CELLS 审中-公开
标题翻译：编程非易失性存储包括减少其他记忆细胞的影响
公开(公告)号：WO2011133404A1
公开(公告)日：2011-10-27
申请号：PCT/US2011/032575
申请日：2011-04-14
申请人： SANDISK CORPORATION , DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
发明人： DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/3459 , G11C2211/5621 , G11C2211/5622
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，使用随时间增加的编程信号将第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，使用已经响应于第一触发而被大幅度降低的编程信号，将第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起编程，响应于第二触发而使编程信号升高。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

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