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1. 发明专利

JP2011077521A Vertical nonvolatile memory device and method for manufacturing the same 有权
标题翻译：垂直非易失性存储器件及其制造方法
公开(公告)号：JP2011077521A
公开(公告)日：2011-04-14
申请号：JP2010207858
申请日：2010-09-16
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM YOUNG-HOO , LEE HYO-SAN , BAE SANG-WON , IN FUGEN , LEE KUN-TACK
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11578 , H01L27/11556 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a vertical nonvolatile memory device and a manufacturing method therefor. SOLUTION: The vertical nonvolatile memory device includes filler-shaped monocrystalline semiconductor channels that are provided vertically on a semiconductor substrate 100; interlayer insulating films (pattern) 122a to 122e of first to n+1-th level (n is a natural number larger than 1) that are laminated at regular intervals, on the side of the monocrystalline semiconductor channels; electric charge trap films 170, provided on the interlayer insulating films (pattern) 122a to 122e; a blocking-insulating films 175 provided on the electrical charge trap films 170; first to n-th layer control gate electrode patterns 185a to 185d provided on the blocking insulating films 175; and GSL and SSL gates free of an electric charge trap layer disposed on the lowermost and at uppermost interlayer insulating layers. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种垂直非易失性存储装置及其制造方法。解决方案：垂直非易失性存储器件包括垂直设置在半导体衬底100上的填充型单晶半导体沟道; 在单晶半导体通道一侧以规则间隔层叠第一至第n + 1层的层间绝缘膜（图案）122a至122e（n为大于1的自然数）设置在层间绝缘膜（图案）122a〜122e上的电荷陷阱膜170; 设置在电荷捕获膜170上的阻挡绝缘膜175; 设置在阻挡绝缘膜175上的第一至第n层控制栅电极图案185a至185d; 并且GSL和SSL门没有设置在最下层和最上层的层间绝缘层上的电荷陷阱层。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2006140471A Etching solution to remove dielectric film with low permittivity, and etching method of the film using the solution 审中-公开
标题翻译：蚀刻解决方案去除低电容的电介质膜，以及使用溶液的电影的蚀刻方法
公开(公告)号：JP2006140471A
公开(公告)日：2006-06-01
申请号：JP2005316913
申请日：2005-10-31
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIN BIEI , LEE HYO-SAN , KO IKUZEN , OH JUN-HWAN , LEE SANG-MIN
IPC分类号： H01L21/306 , C23F1/24
CPC分类号： C09K13/08 , H01L21/31111
摘要： PROBLEM TO BE SOLVED: To provide an etching solution to remove a dielectric film with a low permittivity, and the etching method of the film using the solution.
SOLUTION: The etching solution to etch the dielectric film having a low permittivity contains an oxidizing agent to oxidize the dielectric film having a low permittivity and an oxide-etching agent to remove the oxide. Use of the etching solution allows to remove a dielectric film having a low permittivity simply in one process.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种蚀刻溶液以去除具有低介电常数的电介质膜，以及使用该溶液的膜的蚀刻方法。解决方案：蚀刻具有低介电常数的电介质膜的蚀刻溶液含有氧化剂以氧化具有低介电常数的介电膜和氧化物蚀刻剂以除去氧化物。使用蚀刻溶液允许简单地在一个工艺中去除具有低介电常数的介电膜。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006310845A Method for manufacturing flash memory having u-shaped floating gate 审中-公开
标题翻译：用于制造具有U型浮动门的闪存的方法
公开(公告)号：JP2006310845A
公开(公告)日：2006-11-09
申请号：JP2006116127
申请日：2006-04-19
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： HAN JEONG-NAM , KIM DONG-CHAN , KANG CHANG-JIN , CHI KYOKYU , SHIM WOO-GWAN , LEE HYO-SAN , HONG CHANGKI , CHOI SANG-JUN
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a flash memory having a U-shaped floating gate.
SOLUTION: After an element isolation film is formed with the top surface and part of both side surfaces protruding from the surface of a substrate, a tunnel oxide film is formed on the substrate between the element isolation films. After a conductive film is formed on the tunnel oxide film so as to have a thickness with which the gap is not filled between the element isolation films, a polishing sacrifice film is formed on the conductive film. A U-shaped self-aligned floating gate is formed between the element isolation films by removing the polishing sacrifice film and the conductive film on the element isolation film and at the same time, and the polishing sacrifice film pattern is left on the floating gate. The walls on both the sides of the floating gate are exposed by recessing the element isolation film using the polishing sacrifice film pattern as a mask, and, by selectively removing the polishing sacrifice film pattern with respect to the floating gate, the top surface of the floating gate is exposed.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于制造具有U形浮动栅极的闪速存储器的方法。解决方案：在元件隔离膜形成有从基板的表面突出的顶表面和两个侧表面的一部分之后，在元件隔离膜之间的衬底上形成隧道氧化膜。在隧道氧化膜上形成导电膜以使元件隔离膜之间没有填充间隙的厚度之后，在导电膜上形成抛光牺牲膜。通过去除元件隔离膜上的抛光牺牲膜和导电膜，同时在元件隔离膜之间形成U形自对准浮栅，抛光牺牲膜图案留在浮栅上。通过使用抛光牺牲膜图案作为掩模使元件隔离膜凹陷来暴露浮栅的两侧的壁，并且通过相对于浮栅选择性地去除抛光牺牲膜图案，浮动门被暴露。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2005303305A Paa system etching liquid, etching method utilizing it, and structure of resultant material 有权
标题翻译： PAA系统蚀刻液，利用其的蚀刻方法和结构材料的结构
公开(公告)号：JP2005303305A
公开(公告)日：2005-10-27
申请号：JP2005112763
申请日：2005-04-08
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE HYO-SAN , KO HYUNG-HO , HONG CHANGKI , CHOI SANG-JUN
IPC分类号： H01L21/308 , C09K13/08 , C23F1/24 , G11C8/02 , H01L21/306 , H01L21/3213 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L27/108 , H01L29/786
CPC分类号： H01L29/78696 , C09K13/08 , H01L21/30604 , H01L21/32134 , H01L21/32136 , H01L21/32137 , H01L21/823807 , H01L21/823828 , H01L27/10826 , H01L27/10852 , H01L28/91 , H01L29/42392 , H01L29/66772 , H01L29/66795 , H01L29/66818 , H01L29/785
摘要： PROBLEM TO BE SOLVED: To provide a peracetic acid (PAA) system etching liquid, an etching method utilizing it, and a structure of a resultant material. SOLUTION: A composition for wet etching includes a peracetic acid and a fluorinated acid, and also, substantially includes SiGe for a PMOS transistor of a CMOS element, SiGe for an NMOS transistor of the CMOS element with an etching rate equal to that of Si, and a relative amount of an oxidizer in a composition sufficient for securing the etching rate of Si. The composition for wet etching is called as the PAA system etching liquid hereafter and used for manufacturing an electrode for a CMOS, an MBCFET, and a capacitor. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供过乙酸（PAA）系统蚀刻液，利用其的蚀刻方法和所得材料的结构。解决方案：用于湿蚀刻的组合物包括过乙酸和氟化酸，并且还基本包括用于CMOS元件的PMOS晶体管的SiGe，CMOS元件的NMOS晶体管的SiGe，其蚀刻速率等于的Si，以及足以确保Si的蚀刻速率的组合物中的氧化剂的相对量。用于湿蚀刻的组合物在下文中被称为PAA系统蚀刻液，并用于制造用于CMOS的电极，MBCFET和电容器。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006295190A Cleaning liquid and method for forming metallic pattern of semiconductor device using the same 审中-公开
标题翻译：用于形成使用其的半导体器件的金属图案的清洁液体和方法
公开(公告)号：JP2006295190A
公开(公告)日：2006-10-26
申请号：JP2006110175
申请日：2006-04-12
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE HYO-SAN , KIM SANG-YONG , HONG CHANGKI , CHOI SANG-JUN , SHIM WOO-GWAN , PARK IM-SOO , BAEK KUI-JONG , HAN WOONG , LIM JUNG HUN , LEE SANG WON , KIM SUNG BAE , KIN GENTAKU
IPC分类号： H01L21/304
CPC分类号： H01L21/0206 , C09K13/08 , C23G1/10 , H01L21/02071
摘要： PROBLEM TO BE SOLVED: To provide a cleaning liquid and a method for forming a metallic pattern of a semiconductor device. SOLUTION: The cleaning liquid contains acetic acid, inorganic acid, a fluorine compound, and deionized water, and the method for forming a metallic pattern uses the same. The cleaning liquid may further contain a corrosion inhibitor, a chelating agent, or a combination of these. For the metallic pattern formation method, a metal film composed of Ru is formed on a substrate. Part of the metal film is dry-etched to form a metal pattern. Using a compound liquid containing acetic acid, inorganic acid, a fluorine compound, and deionized water, the metal film pattern is cleaned to remove etching by-product layers around the metal film pattern. When an oxide film pattern is used as an etching mask to form a metal film pattern, the oxide film pattern is formed and then, the cleaning liquid is used to remove the etching by-product layers around the oxide film pattern before dry-etching the metal film. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种清洁液体和形成半导体器件的金属图案的方法。解决方案：清洗液含有乙酸，无机酸，氟化合物和去离子水，并且形成金属图案的方法使用它们。清洗液还可以含有腐蚀抑制剂，螯合剂或它们的组合。对于金属图案形成方法，在基板上形成由Ru构成的金属膜。金属膜的一部分被干蚀刻以形成金属图案。使用含有乙酸，无机酸，氟化合物和去离子水的复合液体，清洗金属膜图案以去除金属膜图案周围的蚀刻副产物层。当使用氧化膜图案作为蚀刻掩模以形成金属膜图案时，形成氧化膜图案，然后使用清洗液去除干蚀刻之前的氧化膜图案周围的蚀刻副产物层金属膜。版权所有（C）2007，JPO＆INPIT

6. 发明专利

DE102010037434B8 Verfahren zur Herstellung einer nicht-flüchtigen Speichervorrichtung vom vertikalen Typ 未知
公开(公告)号：DE102010037434B8
公开(公告)日：2020-04-30
申请号：DE102010037434
申请日：2010-09-09
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM YOUNG-HOO , LEE HYO-SAN , BAE SANG-WON , YOON BO-UN , LEE KUN-TACK
IPC分类号： H01L27/11578 , G11C16/00 , H01L27/1157 , H01L27/11582

7. 发明专利

DE102010037434B4 Verfahren zur Herstellung einer nicht-flüchtigen Speichervorrichtung vom vertikalen Typ 未知
公开(公告)号：DE102010037434B4
公开(公告)日：2020-03-05
申请号：DE102010037434
申请日：2010-09-09
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM YOUNG-HOO , LEE HYO-SAN , BAE SANG-WON , YOON BO-UN , LEE KUN-TACK
IPC分类号： H01L27/11578 , G11C16/00 , H01L27/1157 , H01L27/11582
摘要： Verfahren zur Herstellung einer nicht-flüchtigen Speichervorrichtung vom vertikalen Typ, aufweisend:Ausbilden eines Störstellenbereichs (105; 230) in einem Halbleitersubstrat (100; 200);Ausbilden einer unteren Isolierschicht (110; 235) auf dem Störstellenbereich (105; 230);Ausbilden einer unteren Elektrodenschicht (115; 240) auf der unteren Isolierschicht (110; 235);wiederholtes Ausbilden von Isolierzwischenschichten (120a-120e; 245a-245e) und Opferschichten (125a-125d; 250a-250e) auf der unteren Elektrodenschicht (115; 240);Ausbilden einer oberen Elektrodenschicht (130; 255) auf einer obersten Isolierzwischenschicht (120e; 245e);Ausbilden einer Kanalausnehmung (140; 260) in den wiederholt gestapelten Schichten, um Isolierzwischenschichtmuster (122a-122e; 247a-247e) und Opferschichtmuster (127a-127d; 252a-252d) zu bilden, wobei der Störstellenbereich (105; 230) durch die Kanalausnehmung (140; 260) freigelegt wird;Ausbilden einer Tunneloxidschicht (145; 265) auf einer Seitenwand der Kanalausnehmung (140; 260);Ausbilden eines einkristallinen Halbleitermusters (150; 270) auf der Tunneloxidschicht (145; 265) in der Kanalausnehmung (140; 260);Ausbilden eines Isolierschichtmusters (155; 275) in der Kanalausnehmung (140; 260);Entfernen der Opferschichtmuster (127a-127d; 252a-252d), um die Tunneloxidschicht (145; 265) freizulegen;Ausbilden einer Ladungsspeicherschicht (170; 285) und einer blockierenden dielektrischen Schicht (175; 290) auf der Tunneloxidschicht (145; 265); undAusbilden von Steuergatemustern (185a-185d; 295a-295d) auf der blockierenden dielektrischen Schicht (175; 290) zwischen den Isolierzwischenschichtmustern (122a-122e; 247a-247e).

8. 发明专利

DE102005012356B4 未知
公开(公告)号：DE102005012356B4
公开(公告)日：2009-09-17
申请号：DE102005012356
申请日：2005-03-17
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： LEE HYO-SAN , KO HYUNG-HO , HONG CHANG-KI , CHOI SANG-JUN
IPC分类号： H01L21/306 , C09K13/08 , H01L21/308 , C23F1/24 , G11C8/02 , H01L21/3213 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L27/108 , H01L29/786
摘要： Wet-etch composition comprises an oxidant exhibiting a significantly greater etching rate for silicon-germanium relative to silicon and a fluorinated acid. The relative amount of the oxidant in the composition being sufficient to ensure an etch rate ratio of silicon-germanium (SiGe):silicon (Si) for PMOS transistors of the CMOS device. Independent claims are included for: (a) manufacturing semiconductor device having a multi-bridge-channel field effect transistor (MBCFET) structure involving providing a structure having stacked Si bridge layers and SiGe interbridge layers, respectively and supported by at least one bridge-support structure; applying an etchant composition to side surfaces of the SiGe bridge layers, the etchant including peracetic acid (PAA) and a fluorinated acid. The relative amount of the PAA in the composition being sufficient to yield an etch rate ratio of SiGe:Si for NMOS transistors of the MBCFET device that is substantially the same as an etch rate ratio of SiGe:Si for PMOS transistors of the MBCFET device; (b) selectively removing SiGe from between layers of silicon involving providing a substrate, forming a stack of alternating layers of SiGe and Si on the substrate, exposing side surfaces of the stack, applying an etchant composition to side surfaces of the SiGe bridge layer, the etchant including PAA and a fluorinated acid. The relative amount of the PAA in the composition being sufficient to yield an etch rate ratio of SiGe:Si for NMOS transistors that is substantially the same as an etch rate ratio of SiGe:Si for PMOS transistors; (c) manufacturing a semiconductor capacitor involving providing a substrate that includes a conductive region, forming a SiGe layer on the substrate, forming a storage node hole in the SiGe layer to expose the conductive region in the substrate, forming a silicon layer on the SiGe layer and on the exposed conductive region of the substrate, forming an insulating layer on the silicon layer, selectively removing portions of silicon layer and insulating layer to define a storage electrode, applying an etchant composition to side surfaces of the SiGe layer, the etchant including PAA and fluorinated acid; (d) manufacturing (M1) an integrated circuit CMOS field effect transistor involving forming a pre-active pattern on a surface of a substrate, the pre-active pattern including a series of SiGe inter-bridge layers and Si bridge layers stacked alternately upon each other; forming source/drain regions on the substrate, at opposite ends of the pre-active pattern; selectively removing, using an etchant, the number of interbridge layers, to form a number of tunnels passing through the pre-active pattern to define an active channel pattern including the tunnels and a number of bridges including the bridge layers, the etchant exhibiting an etch rate ratio of SiGe:Si for NMOS transistors of a CMOS device that is substantially the same as an etch rate ratio of SiGe:Si for PMOS transistors of the CMOS device and forming a gate electrode in the tunnels and surrounding the bridges; and (e) forming (F1) an electrode of a capacitor for a semiconductor device involving forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a conductive pad; forming an etch stop layer on the interlayer insulating layer, forming a first moulding layer of SiGe on the etch stop layer, forming a storage node opening in the first moulding layer, depositing conductive layer of Si on the first moulding layer and on the sidewalls and the bottom of the opening, forming a second molding layer of SiGe on the conductive layer, planarizing the resulting structure until the top surface of the first molding layer is exposed, partially removing an upper portion of the first and second molding layers using a PAA-based etchant to expose a sidewall portion of the conductive layer, thinning the exposed sidewall portion and removing the remaining portion of the first and the second molding layers .

9. 发明专利

DE102004029077A1 Removing photoresist from substrate involves treating photoresist with supercritical carbon dioxide, treating photoresist with ozone-based reactant and removing the photoresist with deionized water 未知
公开(公告)号：DE102004029077A1
公开(公告)日：2005-02-24
申请号：DE102004029077
申请日：2004-06-16
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HAN DONG-GYUN , CHOI SANG-JUN , KO HYUNG-HO , LEE HYO-SAN , HAN WOO-SUNG , HONG CHANG-KI
IPC分类号： G03F7/42 , G03F7/36 , H01L21/027 , H01L21/304
摘要： Removing photoresist from a substrate (110) involves treating the photoresist with supercritical carbon dioxide (300) to cause swelling, cracking or delamination of the photoresist, treating photoresist with ozone-based reactant (400) to chemically alter the photoresist and subsequently removing the photoresist with deionized water (500). The photoresist includes at least one organic residue or organic contaminants. An independent claim is included for an apparatus for removing the photoresist from a substrate.

10. 发明专利

DE102010037434A1 Halbleitervorrichtung vom vertikalen Typ und Verfahren zum Herstellen derselben 未知
公开(公告)号：DE102010037434A1
公开(公告)日：2011-03-31
申请号：DE102010037434
申请日：2010-09-09
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM YOUNG-HOO , LEE HYO-SAN , BAE SANG-WON , YOON BO-UN , LEE KUN-TACK
IPC分类号： H01L27/115 , G11C16/00 , H01L21/8247

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