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1. 发明专利

JP2012114445A Method for manufacturing semiconductor having metal gate electrode 有权
标题翻译：制造具有金属门电极的半导体的方法
公开(公告)号：JP2012114445A
公开(公告)日：2012-06-14
申请号：JP2011256006
申请日：2011-11-24
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHOI SUK-HUN , IN FUGEN , BAEK JAE-JIK , CHO BYEONG-KWON
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/32139 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor element, capable of optimizing characteristics of a CMOS integrated circuit without yield reduction.SOLUTION: An interlayer insulating film 15 is formed to have a first groove 15a and a second groove 15b respectively formed in a first region A and a second region B on a semiconductor substrate 1. Next, a laminated metal film 22 is formed on the semiconductor substrate 1, and a non-photosensitive flattened film 23 is formed on the laminated metal film 22 in a manner to fill the first groove 15a and the second groove 15b. The flattened film 23 in the first region A is selectively removed by dry etching, so that the laminated metal film 22 in the first region A is exposed and a flattened film pattern 23p is formed to cover the laminated metal film 22 in the second region B. With this, an uppermost metal film in the first region A can be removed, and accordingly, a first metal gate electrode and a second metal gate electrode having different work functions can be formed without yield reduction.
摘要翻译：要解决的问题：提供一种能够优化CMOS集成电路的特性而不降低成本的半导体元件的制造方法。解决方案：层间绝缘膜15形成为具有分别形成在半导体基板1上的第一区域A和第二区域B中的第一槽15a和第二槽15b。接下来，形成层压金属膜22 在半导体基板1上，并且以填充第一槽15a和第二槽15b的方式在层压金属膜22上形成非感光性平坦化膜23。通过干蚀刻选择性地去除第一区域A中的扁平薄膜23，使得第一区域A中的层压金属膜22暴露，并且形成平坦的薄膜图案23p以覆盖第二区域B中的层叠金属膜22 由此，可以除去第一区域A中的最上面的金属膜，因此，可以形成具有不同功函数的第一金属栅电极和第二金属栅电极，而不降低成品率。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2007096321A Method of forming self-aligned contact pad using chemical mechanical polishing process 审中-公开
标题翻译：使用化学机械抛光工艺形成自对准接触垫的方法
公开(公告)号：JP2007096321A
公开(公告)日：2007-04-12
申请号：JP2006263157
申请日：2006-09-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM HO-YOUNG , HONG CHANGKI , IN FUGEN , BOKU SHUNSO
IPC分类号： H01L21/768 , B24B37/013 , H01L21/304 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10873 , H01L27/10885
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a self-aligned contact pad using a Chemical Mechanical Polishing process. SOLUTION: The method includes steps of: forming stacks of a conductive line and an insulating capping layer, spacers, and insulating layers configured to expose the top of the capping layer, on a semiconductor substrate; selectively, partially etching the capping layers to form damascene grooves; forming a first etching mask to fill the grooves and then forming a second etching mask having opened regions to be exposed across a plurality of portions of the first etching mask and insulating layer; etching selectively the portions of the insulating layer exposed by the second and first etching masks to form a plurality of opened holes together; removing the second etching mask and then forming conductive layers that fill the opened holes; and performing CMP using the capping layer as a polishing end point, wherein the remaining first etching mask also is processed to be removed during the polishing so that node-separation can be effected with self-aligned contact pads. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供使用化学机械抛光工艺形成自对准接触垫的方法。解决方案：该方法包括以下步骤：在半导体衬底上形成导线和绝缘覆盖层，间隔物和被配置为暴露覆盖层顶部的绝缘层的叠层; 选择性地，部分蚀刻封盖层以形成镶嵌槽; 形成第一蚀刻掩模以填充所述凹槽，然后形成具有待暴露在所述第一蚀刻掩模和绝缘层的多个部分上的开放区域的第二蚀刻掩模; 选择性地蚀刻由第二和第一蚀刻掩模暴露的绝缘层的部分，以一起形成多个开孔; 去除第二蚀刻掩模，然后形成填充打开的孔的导电层; 并且使用覆盖层进行CMP作为抛光终点，其中在抛光期间，剩余的第一蚀刻掩模也被处理以除去，以便可以利用自对准接触焊盘实现节点分离。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2008166802A Manufacturing method of semiconductor device having channel film 有权
标题翻译：具有通道膜的半导体器件的制造方法
公开(公告)号：JP2008166802A
公开(公告)日：2008-07-17
申请号：JP2007336416
申请日：2007-12-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LIM JONG HEUN , HONG CHANGKI , IN FUGEN , YUN SEONG KYU , CHOI SUK-HUN , HAN SANG YEOB
IPC分类号： H01L21/20 , H01L21/28 , H01L21/768 , H01L21/8234 , H01L21/8244 , H01L27/00 , H01L27/088 , H01L27/11 , H01L29/417
CPC分类号： H01L21/02675 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, with a channel film having small crystal defects and proper surface roughness characteristics. SOLUTION: The manufacturing method of a semiconductor with a channel film comprises, first, forming a first single crystal silicon film 110 containing portions extending and protruding from its upper surface on a single crystal silicon substrate 100; forming a sacrificial film 112 on the upper surface of the first single-crystal silicon film 110, subjecting the first single-crystal silicon film 110 and the sacrificial film 112 to a primary polishing so that the protruded portions of the first single-crystal silicon film 110 and a part of the sacrificial film 112 are removed, to form a second single-crystal silicon film and a sacrificial film pattern, removing the sacrificial film pattern, and polishing the second single-crystal silicon film to form a channel silicon film. According to this process, the polishing thickness of the single-crystal silicon film can be reduced, and the channel silicon film has a proper surface roughness characteristics and the thickness becomes flat. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件的制造方法，其具有晶体缺陷小和表面粗糙度适当的沟道膜。解决方案：具有沟道膜的半导体的制造方法首先包括在单晶硅衬底100上形成从其上表面延伸并突出的部分的第一单晶硅膜110; 在第一单晶硅膜110的上表面上形成牺牲膜112，对第一单晶硅膜110和牺牲膜112进行一次抛光，使得第一单晶硅膜的突出部分 110和牺牲膜112的一部分被去除，以形成第二单晶硅膜和牺牲膜图案，去除牺牲膜图案，并抛光第二单晶硅膜以形成沟道硅膜。根据该工序，可以降低单晶硅膜的研磨厚度，并且通道硅膜具有适当的表面粗糙度特性，并且厚度变得平坦。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007005820A Cmp slurry, cmp method, and shallow-trench isolation method using same 审中-公开
标题翻译： CMP浆料，CMP方法和使用该方法的SHALLOW-TRENCH隔离方法
公开(公告)号：JP2007005820A
公开(公告)日：2007-01-11
申请号：JP2006222695
申请日：2006-08-17
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE JONG-WON , LEE JAE-DONG , IN FUGEN , HAH SANG-ROK
IPC分类号： B24B57/02 , H01L21/304 , B24B37/00 , C09G1/02 , C09K3/14 , H01L21/3105
CPC分类号： H01L21/31053 , C09G1/02 , C09K3/1463
摘要： PROBLEM TO BE SOLVED: To provide a CMP (chemical-mechanical polishing) slurry, a CMP method, and a shallow-trench isolation method using the same. SOLUTION: The CMP oxide slurry is composed of polishing particles and an aqueous solution including two or more different passivation agents. Preferably, the aqueous solution contains deionized water, and the polishing particles are of a metal oxide selected from a group including ceria, silica, alumina, titania, zirconia and germania. The first passivation agent can be a cationic, anionic, or nonionic surfactant, and the second passivation agent can be phthalic acid or its salt. For example, the first passivation agent is polyvinyl sulfonate, and the second passivation agent is potassium hydrogen phthalate. Such a slurry exhibits a high dislodging selectivity of an oxide to a silicon nitride film. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供CMP（化学机械抛光）浆料，CMP方法和使用其的浅沟槽隔离方法。解决方案：CMP氧化物浆料由抛光颗粒和包含两种或更多种不同钝化剂的水溶液组成。优选地，水溶液含有去离子水，并且抛光颗粒是选自包括二氧化铈，二氧化硅，氧化铝，二氧化钛，氧化锆和锗的组的金属氧化物。第一钝化剂可以是阳离子，阴离子或非离子表面活性剂，第二钝化剂可以是邻苯二甲酸或其盐。例如，第一钝化剂是聚乙烯基磺酸盐，第二钝化剂是邻苯二甲酸氢钾。这种浆料表现出氧化物对氮化硅膜的高脱离选择性。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2005353929A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2005353929A
公开(公告)日：2005-12-22
申请号：JP2004174930
申请日：2004-06-14
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： IN FUGEN , KONDO SEIICHI , TOKIFUJI SHUNICHI
IPC分类号： H01L21/3205 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To provide a method of restraining peeling from sharply spreading owing to the ductility of Cu at the time of polishing of the Cu.
SOLUTION: The method comprises a low-k film formation process (S104) of forming a low-k film on a substrate using a dielectric insulating material, an SiO
2 film formation process (S108) for forming an SiO
2 film on the low-k film, an SiO
2 film polishing process (S110) of polishing the SiO
2 film; an opening part formation process (S112) of forming an opening part after the polishing process, a deposition process (S114 to S118) of depositing a conductive material on the opening part and the SiO
2 film, and a conductive material polishing process (S120 to S122) of polishing the conductive material.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种抑制由于Cu的抛光时Cu的延展性而使剥离急剧扩展的方法。解决方案：该方法包括使用介电绝缘材料，SiO 2 成膜工艺（S108）在衬底上形成低k膜的低k成膜工艺（S104）用于在低k膜上形成SiO 2 SB SiO 2薄膜，研磨SiO 2 SBS薄膜的SiO 2 SBO 2薄膜研磨工艺（S110）; 在研磨处理之后形成开口部的开口部形成工序（S112），在开口部和SiO＆lt; SB＆gt; 2＆lt; SB＆gt;膜之间沉积导电材料的沉积工艺（S114至S118），以及导电材料抛光工艺（S120至S122）。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2011077521A Vertical nonvolatile memory device and method for manufacturing the same 有权
标题翻译：垂直非易失性存储器件及其制造方法
公开(公告)号：JP2011077521A
公开(公告)日：2011-04-14
申请号：JP2010207858
申请日：2010-09-16
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM YOUNG-HOO , LEE HYO-SAN , BAE SANG-WON , IN FUGEN , LEE KUN-TACK
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11578 , H01L27/11556 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a vertical nonvolatile memory device and a manufacturing method therefor. SOLUTION: The vertical nonvolatile memory device includes filler-shaped monocrystalline semiconductor channels that are provided vertically on a semiconductor substrate 100; interlayer insulating films (pattern) 122a to 122e of first to n+1-th level (n is a natural number larger than 1) that are laminated at regular intervals, on the side of the monocrystalline semiconductor channels; electric charge trap films 170, provided on the interlayer insulating films (pattern) 122a to 122e; a blocking-insulating films 175 provided on the electrical charge trap films 170; first to n-th layer control gate electrode patterns 185a to 185d provided on the blocking insulating films 175; and GSL and SSL gates free of an electric charge trap layer disposed on the lowermost and at uppermost interlayer insulating layers. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种垂直非易失性存储装置及其制造方法。解决方案：垂直非易失性存储器件包括垂直设置在半导体衬底100上的填充型单晶半导体沟道; 在单晶半导体通道一侧以规则间隔层叠第一至第n + 1层的层间绝缘膜（图案）122a至122e（n为大于1的自然数）设置在层间绝缘膜（图案）122a〜122e上的电荷陷阱膜170; 设置在电荷捕获膜170上的阻挡绝缘膜175; 设置在阻挡绝缘膜175上的第一至第n层控制栅电极图案185a至185d; 并且GSL和SSL门没有设置在最下层和最上层的层间绝缘层上的电荷陷阱层。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2008205456A Method of forming semiconductor element 审中-公开
标题翻译：形成半导体元件的方法
公开(公告)号：JP2008205456A
公开(公告)日：2008-09-04
申请号：JP2008023038
申请日：2008-02-01
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LIM JONG HEUN , HONG CHANGKI , IN FUGEN , BAE DAE-LOK , YUN SEONG KYU , CHOI SUK-HUN
IPC分类号： H01L21/76 , H01L21/02 , H01L21/762 , H01L21/8234 , H01L27/00 , H01L27/08 , H01L27/088 , H01L27/12
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/8221
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a semiconductor element having a wide single crystal semiconductor region without using a photolithography process.
SOLUTION: Bonding surfaces which are arranged mutually separately are formed on a first substrate 150. Then a second substrate 100 is joined to the bonding surfaces of the first substrate 150. Then the second substrate 100 is separated in such a way that each of semiconductor regions of the second substrate 100 is left on each of the bonding surfaces which are arranged mutually separately on an upper surface of the first substrate 150. The bonding surfaces include a surface of at least one insulating region on the first substrate 150. At least one active region is formed at least in one of the semiconductor regions. An element isolating region is formed in such a way that it adjoins at least one of the semiconductor regions. These steps dispense with carrying out separately a photolithography process and the process of forming the semiconductor element is simplified.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在不使用光刻工艺的情况下形成具有宽单晶半导体区域的半导体元件的方法。解决方案：在第一基板150上形成相互分开相互排列的接合表面。然后，第二基板100接合到第一基板150的接合表面。然后，第二基板100以每个第二基板100的半导体区域被保留在相互分离地布置在第一基板150的上表面上的每个接合表面上。接合表面包括在第一基板150上的至少一个绝缘区域的表面。至少在一个半导体区域中形成至少一个有源区。元件隔离区域以与半导体区域中的至少一个相邻的方式形成。省略了分别执行光刻工艺和形成半导体元件的工艺的这些步骤。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2001148360A CHEMICAL AND MECHANICAL GRINDING SLURRY AND GRINDING METHOD 失效
公开(公告)号：JP2001148360A
公开(公告)日：2001-05-29
申请号：JP2000292725
申请日：2000-09-26
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： RI SHOGEN , IN FUGEN
IPC分类号： B24B1/00 , B24B37/00 , B24C1/00 , C09K3/14 , C09K13/04 , H01L21/304 , H01L21/306
摘要： PROBLEM TO BE SOLVED: To provide a slurry with good quality and safety in a CMP method for reducing an added oxidant with a metal removing speed as fast as a conventional case and reducing the productive cost, and provide a CMP method for adjusting metal removing speed when the improved slurry is used. SOLUTION: A slurry for grinding a metallic layer in a semiconductor integrated circuit chemically and mechanically contains an aqueous agent made of many kinds of oxidants and a grinding agent. At least one of oxidant is a first oxidant for oxidizing the other oxidizing agents. At least another one is a second oxidant for oxidizing the metallic layer. Then, the second oxidant is reduced itself in a repeated cycle of the oxidation by the first oxidant. The slurry solution is made strong acid.

9. 发明专利

JP2002313760A CHEMICAL MECHANICAL POLISHING SLURRY, CHEMICAL MECHANICAL POLISHING METHOD, AND SHALLOW TRENCH ELEMENT SEPARATION METHOD ADOPTING THE SAME 审中-公开
公开(公告)号：JP2002313760A
公开(公告)日：2002-10-25
申请号：JP2001392645
申请日：2001-12-25
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： LEE JONG-WON , LEE JAE-DONG , IN FUGEN , HAH SANG-ROK
IPC分类号： B24B57/02 , B24B37/00 , C09G1/02 , C09K3/14 , H01L21/304 , H01L21/3105
摘要： PROBLEM TO BE SOLVED: To provide a chemical mechanical polishing slurry, a chemical mechanical polishing method, and a shallow trench element separation method adopting the same. SOLUTION: A chemical mechanical polishing oxide slurry comprises polishing particles and an aqueous solution containing two or more passivation agents different from each other. Preferably, the aqueous solution contains deionized water, and the polishing particles are a metal oxide selected from a group of ceria, silica, alumina, titania, zirconia, and germanium. The first passivation agent may be an anionic, cationic, or non-ionic surfactant, and the second passivation agent may be phthalic acid and its salt. For example, the first passivation agent is a polyvinyl sulfonic acid and the second passivation agent is potassium hydrodienephthalate. Such slurry indicates a high removal selection ratio of an oxide to a silicon nitride film.

10. 发明专利

JP2002208636A METHOD OF FORMING CONTACT PAD OF SEMICONDUCTOR ELEMENT 审中-公开
公开(公告)号：JP2002208636A
公开(公告)日：2002-07-26
申请号：JP2001336993
申请日：2001-11-01
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK YOUNG-RAE , KIM JUNG-YUP , IN FUGEN , HAH SANG-ROK
IPC分类号： H01L21/28 , H01L21/304 , H01L21/31 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/088 , H01L27/108 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a contact pad of a semiconductor element which enables to suppress short-circuiting between a bit line and a gate by simplifying processes and thus suppressing the loss of an insulation film at the upper part of the gate, and to suppress void of the laminated inter- layer insulating film, after forming a gate configuration. SOLUTION: A gate configuration/structure 120 that contains an insulating film at the upper part of the gate, a stop layer 104 and an interlayer insulating film 106 are formed on a semiconductor substrate for a CMP process. In the CMP process, the interlayer insulating film is planarized so that at least insulating film at the upper part of the gate 122 is exposed by using a slurry having a high polishing selective ratio of insulation film at the upper part of the gate 122 and interlayer insulating film 106, and the range in interlayer insulating film 106, where a contact pad 136A is formed, is etched. Then planarization is proceeded by using a slurry having a high polishing selective ratio of insulation film at the upper part of the gate 122 and a conductive material for contact pad 136A in the CMP process for vapor deposition of conductive materials for contact pads.

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