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1. 发明专利

JP2008205456A Method of forming semiconductor element 审中-公开
标题翻译：形成半导体元件的方法
公开(公告)号：JP2008205456A
公开(公告)日：2008-09-04
申请号：JP2008023038
申请日：2008-02-01
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LIM JONG HEUN , HONG CHANGKI , IN FUGEN , BAE DAE-LOK , YUN SEONG KYU , CHOI SUK-HUN
IPC分类号： H01L21/76 , H01L21/02 , H01L21/762 , H01L21/8234 , H01L27/00 , H01L27/08 , H01L27/088 , H01L27/12
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/8221
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a semiconductor element having a wide single crystal semiconductor region without using a photolithography process.
SOLUTION: Bonding surfaces which are arranged mutually separately are formed on a first substrate 150. Then a second substrate 100 is joined to the bonding surfaces of the first substrate 150. Then the second substrate 100 is separated in such a way that each of semiconductor regions of the second substrate 100 is left on each of the bonding surfaces which are arranged mutually separately on an upper surface of the first substrate 150. The bonding surfaces include a surface of at least one insulating region on the first substrate 150. At least one active region is formed at least in one of the semiconductor regions. An element isolating region is formed in such a way that it adjoins at least one of the semiconductor regions. These steps dispense with carrying out separately a photolithography process and the process of forming the semiconductor element is simplified.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在不使用光刻工艺的情况下形成具有宽单晶半导体区域的半导体元件的方法。解决方案：在第一基板150上形成相互分开相互排列的接合表面。然后，第二基板100接合到第一基板150的接合表面。然后，第二基板100以每个第二基板100的半导体区域被保留在相互分离地布置在第一基板150的上表面上的每个接合表面上。接合表面包括在第一基板150上的至少一个绝缘区域的表面。至少在一个半导体区域中形成至少一个有源区。元件隔离区域以与半导体区域中的至少一个相邻的方式形成。省略了分别执行光刻工艺和形成半导体元件的工艺的这些步骤。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008166802A Manufacturing method of semiconductor device having channel film 有权
标题翻译：具有通道膜的半导体器件的制造方法
公开(公告)号：JP2008166802A
公开(公告)日：2008-07-17
申请号：JP2007336416
申请日：2007-12-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LIM JONG HEUN , HONG CHANGKI , IN FUGEN , YUN SEONG KYU , CHOI SUK-HUN , HAN SANG YEOB
IPC分类号： H01L21/20 , H01L21/28 , H01L21/768 , H01L21/8234 , H01L21/8244 , H01L27/00 , H01L27/088 , H01L27/11 , H01L29/417
CPC分类号： H01L21/02675 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, with a channel film having small crystal defects and proper surface roughness characteristics. SOLUTION: The manufacturing method of a semiconductor with a channel film comprises, first, forming a first single crystal silicon film 110 containing portions extending and protruding from its upper surface on a single crystal silicon substrate 100; forming a sacrificial film 112 on the upper surface of the first single-crystal silicon film 110, subjecting the first single-crystal silicon film 110 and the sacrificial film 112 to a primary polishing so that the protruded portions of the first single-crystal silicon film 110 and a part of the sacrificial film 112 are removed, to form a second single-crystal silicon film and a sacrificial film pattern, removing the sacrificial film pattern, and polishing the second single-crystal silicon film to form a channel silicon film. According to this process, the polishing thickness of the single-crystal silicon film can be reduced, and the channel silicon film has a proper surface roughness characteristics and the thickness becomes flat. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件的制造方法，其具有晶体缺陷小和表面粗糙度适当的沟道膜。解决方案：具有沟道膜的半导体的制造方法首先包括在单晶硅衬底100上形成从其上表面延伸并突出的部分的第一单晶硅膜110; 在第一单晶硅膜110的上表面上形成牺牲膜112，对第一单晶硅膜110和牺牲膜112进行一次抛光，使得第一单晶硅膜的突出部分 110和牺牲膜112的一部分被去除，以形成第二单晶硅膜和牺牲膜图案，去除牺牲膜图案，并抛光第二单晶硅膜以形成沟道硅膜。根据该工序，可以降低单晶硅膜的研磨厚度，并且通道硅膜具有适当的表面粗糙度特性，并且厚度变得平坦。版权所有（C）2008，JPO＆INPIT

3. 发明公开

KR20070103921A METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：KR20070103921A
公开(公告)日：2007-10-25
申请号：KR20060035844
申请日：2006-04-20
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YUN SEONG KYU , HONG CHANG KI , YOON BO UN , KIM HO YOUNG , LIM JOUNG HEUN , HAN SANG YEOB
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/76224 , H01L29/785
摘要： A method for fabricating a semiconductor device is provided to suppress the increase of electric potential in electrically independent active pins by an electric field generated by gate patterns. A method for fabricating a semiconductor device includes the steps of: forming a hard mask on a substrate; forming a device isolation trench to define a plurality of active pins(115a) arranged in two dimensions by etching the substrate using the hard mask as an etch mask; forming a device isolation layer(130) filling a space between the device isolation trench and the hard masks; forming a plurality of holes between the active pins by patterning the device isolation layer; forming a plurality of recesses to expose the side walls of the active pins between the buried patterns and the active pins; and forming a plurality of gate patterns filling the recesses and crossing the active pins along a second direction.
摘要翻译：提供一种用于制造半导体器件的方法，以通过栅极图案产生的电场来抑制电独立的有效引脚中的电位的增加。一种制造半导体器件的方法包括以下步骤：在衬底上形成硬掩模; 形成器件隔离沟槽以限定通过使用所述硬掩模作为蚀刻掩模蚀刻所述衬底而在二维中排列的多个有源引脚（115a）形成填充所述器件隔离沟槽和所述硬掩模之间的空间的器件隔离层（130）; 通过图案化所述器件隔离层在所述有源引脚之间形成多个孔; 形成多个凹部以暴露所述有源销在所述掩埋图案和所述有源销之间的侧壁; 以及形成填充所述凹部并沿着第二方向与所述活动销交叉的多个栅极图案。

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