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1. 发明授权

US5590076A Channel hot-carrier page write 失效
标题翻译：频道热门页面写入
公开(公告)号：US5590076A
公开(公告)日：1996-12-31
申请号：US493138
申请日：1995-06-21
申请人： Sameer S. Haddad , Chi Chang , David K. Y. Liu
发明人： Sameer S. Haddad , Chi Chang , David K. Y. Liu
IPC分类号： G11C16/02 , G11C16/10 , G11C7/00
CPC分类号： G11C16/10
摘要： Disclosed herein is a channel hot-carrier page write including an array of stacked gate flash EEPROM memory cells operating in a very low energy programming mode permitting page writing of 1024 bits within a 20-100 .mu.S programming interval. Internal programming voltage levels are derived from on-chip circuits, such as charge pumps, operated from a single +V.sub.CC source. In a preferred embodiment, a cache memory buffers data transfers between a computer bus and the page oriented storage array. In another embodiment, core doping is increased in the channel and drain regions to enhance hot carrier injection and to lower the programming drain voltage. The stacked floating gate structure is shown to exhibit a high programming efficiency in a range from 10.sup.-6 to 10.sup.-4 at drain voltages below 5.2 VDC. In another embodiment AC components of the programming current are minimized by precharging a common source line at the start of a programming cycle.
摘要翻译：本文公开了一种通道热载体页面写入，其包括以非常低能量编程模式操作的堆叠栅极快闪EEPROM存储器单元的阵列，允许在20-100μs编程间隔内1024页的页写入。内部编程电压电平源自片上电路，如电荷泵，由单个+ VCC源运行。在优选实施例中，高速缓冲存储器缓冲计算机总线和面向页面的存储阵列之间的数据传输。在另一个实施例中，在沟道和漏极区域中增加了芯掺杂以增强热载流子注入并降低编程漏极电压。堆叠的浮置栅极结构在低于5.2VDC的漏极电压下表现出在10-6至10-4的范围内的高编程效率。在另一个实施例中，通过在编程周期开始时对公共源极线进行预充电，使编程电流的AC分量最小化。

2. 发明授权

US5517443A Method and system for protecting a stacked gate edge in a semi-conductor device from self aligned source (SAS) etch in a semi-conductor device 失效
标题翻译：用于在半导体器件中保护半导体器件中的堆叠栅极边缘与自对准源（SAS）蚀刻的方法和系统
公开(公告)号：US5517443A
公开(公告)日：1996-05-14
申请号：US460603
申请日：1995-06-01
申请人： David K. Y. Liu , Yu Sun , Chi Chang
发明人： David K. Y. Liu , Yu Sun , Chi Chang
IPC分类号： H01L21/8247 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L27/11526 , H01L27/11536
摘要： A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.
摘要翻译：公开了一种用于保护半导体器件的堆叠栅极边缘的工艺。该方法提供在完成自对准源（SAS）蚀刻之前提供间隔物形成。通过在SAS蚀刻之前提供间隔物形成，隧道氧化物完整性得到很大改善，并且源极结注入轮廓更均匀，因为源区周围的硅不会被去除。

3. 发明授权

US5652155A Method for making semiconductor circuit including non-ESD transistors with reduced degradation due to an impurity implant 失效
标题翻译：制造半导体电路的方法包括由于杂质注入而导致的劣化降低的非ESD晶体管
公开(公告)号：US5652155A
公开(公告)日：1997-07-29
申请号：US550424
申请日：1995-10-30
申请人： David K. Y. Liu , Ming Sang Kwan , Chi Chang
发明人： David K. Y. Liu , Ming Sang Kwan , Chi Chang
IPC分类号： H01L27/02 , H01L21/266
CPC分类号： H01L27/0266 , Y10S438/982
摘要： A method for reducing encroachment of an impurity implant into a channel region in a non-ESD transistor in a semiconductor circuit, the non-ESD transistor receiving both first and second implant dopants, and the circuit including a plurality of ESD transistors includes forming the ESD transistors of the circuit at a predetermined angular offset from the non-ESD transistor, and performing the second dopant implant at a predetermined tilt implant angle, wherein the non-ESD transistor has reduced encroachment of the impurity implant. A plurality of transistors formed on a semiconductor wafer include a plurality of non-ESD transistors, the plurality of non-ESD transistors including spacer regions and impurity implant regions encroaching the spacer regions, and a plurality of ESD transistors, the plurality of ESD transistors formed at a predetermined angular offset from the non-ESD transistors. Further, the plurality of ESD transistors include the spacer regions and impurity implant regions encroaching the spacer regions further than the impurity implant regions of the non-ESD transistors.
摘要翻译：一种用于减少杂质注入侵入半导体电路中的非ESD晶体管中的沟道区域的方法，所述非ESD晶体管接收第一和第二注入掺杂剂，并且包括多个ESD晶体管的电路包括形成ESD 晶体管，其以非ESD晶体管的预定角度偏移，并以预定的倾斜注入角执行第二掺杂剂注入，其中非ESD晶体管具有减少的杂质注入侵入。形成在半导体晶片上的多个晶体管包括多个非ESD晶体管，所述多个非ESD晶体管包括间隔区域和侵入间隔区域的杂质注入区域，以及多个ESD晶体管，所述多个ESD晶体管形成在非ESD晶体管的预定角度偏移处。此外，多个ESD晶体管包括比非ESD晶体管的杂质注入区域更远的间隔区域和杂质注入区域。

4. 发明授权

US5596531A Method for decreasing the discharge time of a flash EPROM cell 失效
标题翻译：降低闪速EPROM单元的放电时间的方法
公开(公告)号：US5596531A
公开(公告)日：1997-01-21
申请号：US450167
申请日：1995-05-25
申请人： David K. Y. Liu , Ming S. Kwan , Chi Chang , Sameer Haddad , Yuan Tang
发明人： David K. Y. Liu , Ming S. Kwan , Chi Chang , Sameer Haddad , Yuan Tang
IPC分类号： G11C16/14 , G11C7/00
CPC分类号： G11C16/14
摘要： The present invention presents methods for reducing the discharge time of a Flash EPROM cell. In one aspect, a method includes the steps of forcing an ultraviolet voltage threshold, UVV.sub.t, below a discharge threshold voltage, V.sub.t. The method further comprises reducing the UVV.sub.t to about 0 V. Further, the method further comprises the step of reducing a core cell implant of a p-type dopant into a substrate of the cell. In a further aspect, a method for decreasing the discharge time includes the steps of providing a core cell implant of a p-type dopant into a surface of a substrate of the cell, and providing a surface doping of an n-type dopant into the core of the substrate, where the core implant reduces punchthrough and the surface doping of an n-type dopant reduces V.sub.t in the cell. In yet another aspect, a method for decreasing a discharge time of a Flash EPROM cell while reducing punchthrough includes the steps of providing a high energy core cell implant of a p type dopant into a substrate of the cell, wherein the core has a doping concentration profile with a low dopant concentration at a surface of the core to reduce UVV.sub.t and a high dopant concentration at lower than the surface to reduce punchthrough.
摘要翻译：本发明提出了减少闪存EPROM单元的放电时间的方法。在一个方面，一种方法包括以下步骤：将紫外线电压阈值UVVt强制在放电阈值电压Vt以下，该方法还包括将UVVt降低到约0V。此外，该方法还包括如下步骤：将p型掺杂剂细胞注入细胞的底物。在另一方面，一种减少放电时间的方法包括以下步骤：将p型掺杂剂的核心单元注入提供到电池的衬底的表面中，并且向n型掺杂剂表面掺杂衬底的芯部，其中芯体植入物减少穿透并且n型掺杂剂的表面掺杂减小了电池中的Vt。在另一方面，一种减少穿透时减少闪存EPROM单元的放电时间的方法包括以下步骤：将ap型掺杂剂的高能核心单元注入提供到电池的衬底中，其中芯具有掺杂浓度分布在芯的表面处具有低掺杂剂浓度以降低UVVt，并且在低于表面的情况下具有高掺杂剂浓度以减少穿透。

5. 发明授权

US5470773A Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch 失效
标题翻译：保护半导体器件中的堆叠栅极边缘的方法不受自对准源（SAS）蚀刻
公开(公告)号：US5470773A
公开(公告)日：1995-11-28
申请号：US233174
申请日：1994-04-25
申请人： David K. Y. Liu , Yu Sun , Chi Chang
发明人： David K. Y. Liu , Yu Sun , Chi Chang
IPC分类号： H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/11536
摘要： A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.
摘要翻译：公开了一种用于保护半导体器件的堆叠栅极边缘的工艺。该方法提供在完成自对准源（SAS）蚀刻之前提供间隔物形成。通过在SAS蚀刻之前提供间隔物形成，隧道氧化物完整性得到很大改善，并且源极结注入轮廓更均匀，因为源区周围的硅不会被去除。

6. 发明授权

US08203861B2 Non-volatile one-time—programmable and multiple-time programmable memory configuration circuit 有权
标题翻译：非易失性一次可编程和多时间可编程存储器配置电路
公开(公告)号：US08203861B2
公开(公告)日：2012-06-19
申请号：US12650238
申请日：2009-12-30
申请人： David K. Y. Liu
发明人： David K. Y. Liu
IPC分类号： G11C17/00
CPC分类号： H03K19/0002 , G11C16/0441 , G11C17/14 , G11C2216/10 , G11C2216/26 , H01L27/11521 , H01L27/11558 , H01L27/11803 , H01L29/7885 , H03K19/177
摘要： A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.
摘要翻译：可编程非易失性配置电路使用以上拉和下拉布置布置的一对非易失性存储器件。非易失性存储器件具有与源极/漏极区域的可变部分重叠的浮动栅极。这允许通过可变电容耦合将器件的编程电压赋予浮置栅极，从而改变器件的状态。本发明可用于存储用于可编程逻辑器件，现场可编程阵列和许多其它应用的配置数据的环境中。

7. 发明授权

US06972234B1 High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage 失效
标题翻译：高栅极二极管击穿电压和穿通电压的高压MOS器件
公开(公告)号：US06972234B1
公开(公告)日：2005-12-06
申请号：US09606252
申请日：2000-06-28
申请人： Raminda U. Madurawe , David K. Y. Liu
发明人： Raminda U. Madurawe , David K. Y. Liu
IPC分类号： H01L21/8238 , H01L27/105 , H01L29/10 , H01L21/336
CPC分类号： H01L21/823807 , H01L27/105 , H01L29/1083
摘要： A method of fabricating CMOS devices suitable for high voltage and low voltage applications, while maintaining minimum channel lengths for the devices. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel effect. The reverse channel effect is optimized for the minimum channel length of the device. Field implants (120), enhancement implants (130), and wells (140) are all formed using a single mask.
摘要翻译：一种制造适合高压和低电压应用的CMOS器件的方法，同时保持器件的最小通道长度。在一个实施例中，口袋植入物（310）形成在引起反向通道效应的最小通道装置中。针对设备的最小通道长度优化了反向通道效应。现场植入物（120），增强植入物（130）和孔（140）均使用单一掩模形成。

8. 发明授权

US06686631B1 Negative differential resistance (NDR) device and method of operating same 有权
标题翻译：负差分电阻（NDR）器件及其操作方法
公开(公告)号：US06686631B1
公开(公告)日：2004-02-03
申请号：US10315741
申请日：2002-12-10
申请人： Tsu-Jae King , David K. Y. Liu
发明人： Tsu-Jae King , David K. Y. Liu
IPC分类号： H01L2972
CPC分类号： B82Y10/00 , G11C5/142 , G11C11/39 , G11C16/04 , H01L21/28273 , H01L21/28282 , H01L27/088 , H01L29/78 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. The MISFET includes a dynamically variable and reversible threshold voltage which is controlled by a source-drain bias. A channel region of the MISFET is doped so as to enhance an electric field associated with the source-drain bias, and thus cause charge carriers to tunnel out of the channel and into a trapping region. A net charge in the trapping region results from the source-drain bias which can be used as an additional control mechanism for conduction in the MISFET.
摘要翻译：公开了在其输出特性（作为漏极电压的函数的漏极电流）中呈现负的差分电阻的n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）。 MISFET包括由源 - 漏偏置控制的动态可变和可逆阈值电压。掺杂MISFET的沟道区域以增强与源极 - 漏极偏压相关联的电场，并且因此导致电荷载流子从沟道中隧道并进入俘获区域。捕获区域中的净电荷来自源极 - 漏极偏置，其可以用作MISFET中的传导的附加控制机制。

9. 发明授权

US5912836A Circuit for detecting both charge gain and charge loss properties in a non-volatile memory array 失效
标题翻译：用于检测非易失性存储器阵列中的电荷增益和电荷损耗特性的电路
公开(公告)号：US5912836A
公开(公告)日：1999-06-15
申请号：US982204
申请日：1997-12-01
申请人： David K. Y. Liu , Kou-Su Chen
发明人： David K. Y. Liu , Kou-Su Chen
IPC分类号： H01L21/66 , G11C16/34 , G11C29/50 , H01L21/8247 , H01L27/115 , G11C16/04
CPC分类号： G11C29/50004 , G11C16/349 , G11C29/50 , G11C29/50016 , G11C16/04 , G11C2029/0403
摘要： A test circuit for observing charge retention characteristics of cells in a flash memory array is disclosed. Unlike prior art structures, the present circuit monitors both charge loss and charge gain of cells in the array. In this way, cells having conduction thresholds below a desired target threshold and cells having conduction thresholds above a desired target threshold can both be observed. The circuit includes a regular memory array, and a mirror array formed with devices having opposite channel types to the regular array. By identifying and evaluating more accurately the threshold characteristics of a particular cell design or cell process, improvements can be made to such designs and processes in a more rapid and optimal fashion.
摘要翻译：公开了一种用于观察闪存阵列中的单元的电荷保持特性的测试电路。不同于现有技术的结构，本电路监测阵列中的电池的电荷损耗和电荷增益。以这种方式，可以观察到具有低于期望目标阈值的导通阈值的细胞和具有高于期望目标阈值的导通阈值的细胞。该电路包括常规存储器阵列，以及由具有与正常阵列相反的通道类型的器件形成的反射镜阵列。通过更准确地识别和评估特定小区设计或小区过程的阈值特性，可以以更快速和最优的方式对这些设计和过程进行改进。

10. 发明授权

US5751631A Flash memory cell and a new method for sensing the content of the new memory cell 失效
公开(公告)号：US5751631A
公开(公告)日：1998-05-12
申请号：US735384
申请日：1996-10-21
申请人： David K. Y. Liu , Wenchi Ting
发明人： David K. Y. Liu , Wenchi Ting
IPC分类号： G11C16/04 , G11C16/26 , H01L27/115 , H01L27/12
CPC分类号： H01L27/1203 , G11C16/0483 , G11C16/26 , H01L27/115
摘要： A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.

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