专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5077691A Flash EEPROM array with negative gate voltage erase operation 失效
标题翻译：具有负栅极电压擦除操作的闪存EEPROM阵列
公开(公告)号：US5077691A
公开(公告)日：1991-12-31
申请号：US426332
申请日：1989-10-23
申请人： Sameer S. Haddad , Chi Chang , Antonio Matalvo , Michael A. Van Buskirk
发明人： Sameer S. Haddad , Chi Chang , Antonio Matalvo , Michael A. Van Buskirk
IPC分类号： G11C16/16 , G11C16/30 , G11C29/00 , G11C29/04 , G11C29/50 , H01L27/115 , H02M3/07
CPC分类号： G11C29/808 , G11C16/16 , G11C16/30 , G11C29/04 , G11C29/50 , G11C29/82 , H01L27/115 , H02M3/073 , G11C16/04 , G11C2029/5006
摘要： A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed between the source region of the cell and the bulk substrate, the generation of hot holes is inhibited and improved performance may be obtained. The source region is preferably single diffused rather than double-diffused so that the cell can occupy a minimum area for a given design rule. The low positive voltage applied to the source is preferably less than or equal to the voltage, V.sub.CC presented at a +5V chip power supply pin. This makes it possible for the +5V pin to directly supply source current during erasure.
摘要翻译：通过将零参考电压施加到电池的体基板，对于电池的控制栅极的相对高的负电压和到电池的源极区域的相对低的正电压来擦除快闪EEPROM单元阵列。由于在电池的源极区域和体基板之间产生相对低的反向电压，所以抑制了热孔的产生并且可以获得改进的性能。源区优选地是单扩散的而不是双扩散的，使得对于给定的设计规则，单元可以占据最小面积。施加到源极的低正电压优选小于或等于在+ 5V芯片电源引脚处呈现的VCC电压。这使得+ 5V引脚可以在擦除期间直接提供电源电流。

2. 发明授权

US5335198A Flash EEPROM array with high endurance 失效
标题翻译：闪存EEPROM阵列具有高耐久性
公开(公告)号：US5335198A
公开(公告)日：1994-08-02
申请号：US57583
申请日：1993-05-06
申请人： Michael A. Van Buskirk , Kevin W. Plouse , Joseph G. Pawletko , Chi Chang , Sameer S. Haddad , Ravi P. Gutala
发明人： Michael A. Van Buskirk , Kevin W. Plouse , Joseph G. Pawletko , Chi Chang , Sameer S. Haddad , Ravi P. Gutala
IPC分类号： G11C16/28 , G11C16/34 , G11C29/00 , G11C29/02 , G11C29/50
CPC分类号： G11C29/82 , G11C16/28 , G11C16/3404 , G11C16/3409 , G11C29/02 , G11C29/025 , G11C29/50 , G11C29/88 , G11C16/04 , G11C2029/5006
摘要： An over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells during programming operations so as to render high endurance. Sensing circuitry (23) is used to detect column leakage current indicative of an over-erased bit. If an over-erased bit is determined, a pulse counter (25) is activated so as to apply programming pulses to the control gate of the selected memory cell so as to program back the negative threshold voltage of the over-erased bit to a positive voltage.
摘要翻译：提供了一种过擦除位校正结构，用于在编程操作期间对闪存EEPROM存储器单元阵列中的擦除过的存储器单元进行校正操作，以使其具有高耐久性。感测电路（23）用于检测指示过擦除位的列泄漏电流。如果确定了过擦除位，则激活脉冲计数器（25），以便将编程脉冲施加到所选存储单元的控制栅极，以便将过擦除位的负阈值电压反馈到正电压。

3. 发明授权

US06808996B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06808996B1
公开(公告)日：2004-10-26
申请号：US09376659
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

4. 发明授权

US06252803B1 Automatic program disturb with intelligent soft programming for flash cells 有权
标题翻译：自动程序干扰与闪存单元的智能软编程
公开(公告)号：US06252803B1
公开(公告)日：2001-06-26
申请号：US09692881
申请日：2000-10-23
申请人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland , Chi Chang
发明人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland , Chi Chang
IPC分类号： G11C1616
CPC分类号： G11C16/16
摘要： A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value. This cycle is repeated until all of those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value are brought above the pre-defined minimum value. The erase method is considered to be finished when there are no memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.
摘要翻译：提供擦除闪存电可擦除可编程只读存储器（EEPROM）设备的方法，其包括多个存储器单元。擦除脉冲被施加到多个存储单元。多个存储器单元被过度验证，并且过高修正脉冲被施加到被过度存储的存储单元附着的位线。重复此循环，直到所有的单元格都被验证为不被过高。多个存储器单元被擦除验证，并且如果存在未存储的存储器单元并且存储器单元再次被擦除验证，则另一个擦除脉冲被施加到存储器单元。重复此循环，直到所有单元格都被验证为不被忽略。在擦除验证完成之后，多个存储器单元被软件程序验证，并且将软编程脉冲施加到具有低于预定义最小值的阈值电压的多个存储单元中的那些存储单元。重复该循环，直到具有低于预定义最小值的阈值电压的多个存储器单元中的所有那些存储器单元高于预定义的最小值。当多个存储单元中没有存储单元的阈值电压低于预先定义的最小值时，擦除方法被认为是完成的。

5. 发明授权

US06492675B1 Flash memory array with dual function control lines and asymmetrical source and drain junctions 失效
标题翻译：具有双功能控制线和不对称源极和漏极结的闪存阵列
公开(公告)号：US06492675B1
公开(公告)日：2002-12-10
申请号：US09008162
申请日：1998-01-16
申请人： Michael A. Van Buskirk , Chi Chang
发明人： Michael A. Van Buskirk , Chi Chang
IPC分类号： H01L2972
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.
摘要翻译：通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。在一组源极/漏极区域中的每一个中形成不对称的第一和第二结，并且施加化学蚀刻以将场氧化物岛形成氧化物间隔物，其将双功能控制线对准到第一和第二结。所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

6. 发明授权

US06894925B1 Flash memory cell programming method and system 有权
标题翻译：闪存单元编程方法和系统
公开(公告)号：US06894925B1
公开(公告)日：2005-05-17
申请号：US10342585
申请日：2003-01-14
申请人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
发明人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
IPC分类号： G11C11/56 , G11C16/04 , H01L29/423 , H01L29/788
CPC分类号： G11C11/5621 , G11C16/0416 , H01L29/42324 , H01L29/7883
摘要： A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.
摘要翻译：提出了一种闪存单元编程系统和方法，其通过提供可偏置的阱（例如，衬底）来促进闪存单元的有效和快速的操作。可偏置阱快闪存储器单元能够以减轻电荷俘获区域（例如浮栅）周围的电介质势垒（例如氧化物）的电荷穿透的方式增加电场强度。本发明的偏压井系统和方法还创建了一个自会聚点，从而在编程操作期间增加了控制，并降低了对擦除过的存储器单元过度校正的可能性。偏置可以帮助硬编程来存储信息和/或软编程以校正过度擦除的影响。偏置还可以减少漏极电压泵上的应力，减少泄漏电流并减少编程持续时间。一些实施方案还包括可偏置控制栅极分量，可偏置源分量和可偏置漏极分量。

7. 发明授权

US06469939B1 Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process 有权
标题翻译：闪存器件在APDE期间提高效率（擦除后的自动程序干扰）过程
公开(公告)号：US06469939B1
公开(公告)日：2002-10-22
申请号：US09969572
申请日：2001-10-01
申请人： Zhigang Wang , Richard Fastow , Sheung-Hee Park , Sameer S. Haddad , Chi Chang
发明人： Zhigang Wang , Richard Fastow , Sheung-Hee Park , Sameer S. Haddad , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/12 , G11C16/3404
摘要： A source resistor or a positive voltage is coupled to the source and a negative bias voltage is applied at the substrate or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected.
摘要翻译：源极电阻或正电压耦合到源极，并且在闪存单元的衬底或p阱处施加负偏置电压，以在编程期间和/或在APDE（擦除后自动程序干扰）处理期间提高效率闪存设备。此外，在用于对闪速存储器件进行编程的系统和方法中，选择多个闪速存储器单元的阵列中的闪存单元进行编程。控制栅极编程电压被施加到所选择的闪速存储器单元的控制栅极，并且位线编程电压通过公共位线端子被施加到所选择的闪存单元的漏极，所述公共位线端子选择闪存的漏极单元格已连接。

8. 发明授权

US06744668B1 Flash memory array with dual function control lines and asymmetrical source and drain junctions 失效
标题翻译：具有双功能控制线和不对称源极和漏极结的闪存阵列
公开(公告)号：US06744668B1
公开(公告)日：2004-06-01
申请号：US10233906
申请日：2002-09-03
申请人： Michael A. Van Buskirk , Chi Chang
发明人： Michael A. Van Buskirk , Chi Chang
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.
摘要翻译：通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。不对称的第一和第二结形成在一组源极/漏极区域中的每一个中，并且施加化学蚀刻以将场氧化物岛形成为将双功能控制线对准到第一和第二结的氧化物间隔物。所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

9. 发明授权

US6001689A Process for fabricating a flash memory with dual function control lines 失效
标题翻译：具有双功能控制线的闪存的制造工艺
公开(公告)号：US6001689A
公开(公告)日：1999-12-14
申请号：US8415
申请日：1998-01-16
申请人： Michael A. Van Buskirk , Chi Chang
发明人： Michael A. Van Buskirk , Chi Chang
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.
摘要翻译：通过一种工艺形成的闪速存储器，其中在硅衬底上形成至少两个平行堆叠的栅极条，使得堆叠的栅极条被场氧化物岛隔开。在一组源极/漏极区域中的每一个中形成不对称的第一和第二结，并且施加化学蚀刻以将场氧化物岛形成氧化物间隔物，其将双功能控制线对准到第一和第二结。所产生的闪速存储器包括多个堆叠的栅极岛，多个堆叠栅极岛的至少一个子集之间的一个或多个源极/漏极区域，每个源极/漏极区域中的第一结，每个源极中的第二结 /漏极区域和源极/漏极区域中的双功能控制线。

10. 发明授权

US5485423A Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS 失效
标题翻译：消除5伏隧道氧化物中循环诱导电子捕获的方法，只有闪存EEPROMS
公开(公告)号：US5485423A
公开(公告)日：1996-01-16
申请号：US320368
申请日：1994-10-11
申请人： Yuan Tang , Chi Chang , Michael A. Van Buskirk , Chung K. Chang
发明人： Yuan Tang , Chi Chang , Michael A. Van Buskirk , Chung K. Chang
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.
摘要翻译：提供了一种用于消除快速EEPROM装置的隧道氧化物中的循环诱导电子捕获的改进方法。在整个擦除周期期间，相对较低的正脉冲电压被施加到EEPROM器件的源极区域。同时，在整个擦除周期期间，向EEPROM器件的控制栅极施加负斜坡电压，从而实现从擦除周期开始到擦除周期结束的平均隧道场。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式