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1. 发明授权

US06653189B1 Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory 有权
标题翻译：源极硼注入和漏极侧MDD植入物用于深亚0.18微米闪存
公开(公告)号：US06653189B1
公开(公告)日：2003-11-25
申请号：US09699711
申请日：2000-10-30
申请人： Sameer Haddad , Yue-song He , Timothy Thurgate , Chi Chang , Mark W. Randolph , Ngaching Wong
发明人： Sameer Haddad , Yue-song He , Timothy Thurgate , Chi Chang , Mark W. Randolph , Ngaching Wong
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L29/66833
摘要： One aspect of the present invention relates to a method of making a flash memory cell, involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; forming a MDD mask over the substrate, the MDD mask covering the source lines and having openings corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region in the substrate adjacent the flash memory cell.
摘要翻译：本发明的一个方面涉及一种制造闪存单元的方法，包括以下步骤：在其上提供闪存单元; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 在衬底上形成MDD掩模，MDD掩模覆盖源极线并具有对应于漏极线的开口; 以及植入第二类型的介质剂量漏极注入，以在与所述闪存单元相邻的所述衬底中形成漏极区域。

2. 发明授权

US06958272B2 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
标题翻译：袖珍种植体用于SONOS存储器单元的互补位干扰改进和充电改进
公开(公告)号：US06958272B2
公开(公告)日：2005-10-25
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
发明人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。最初，电荷俘获电介质层的一部分形成在衬底上，并且在电荷俘获电介质层的部分上形成抗蚀剂。抗蚀剂被图案化，并且以一定角度执行凹穴注入以在衬底内建立口袋植入物。然后执行位线注入以在衬底内建立掩埋位线。然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层。在剩余的电荷俘获电介质层中形成字线材料，并且被图案化以形成覆盖在位线上的字线。口袋种植体用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

3. 发明授权

US06911704B2 Memory cell array with staggered local inter-connect structure 失效
公开(公告)号：US06911704B2
公开(公告)日：2005-06-28
申请号：US10685044
申请日：2003-10-14
申请人： Mark W. Randolph , Sameer S. Haddad , Timothy Thurgate , Richard Fastow
发明人： Mark W. Randolph , Sameer S. Haddad , Timothy Thurgate , Richard Fastow
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L27/082
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.

4. 发明授权

US06906959B2 Method and system for erasing a nitride memory device 有权
标题翻译：擦除氮化物存储器件的方法和系统
公开(公告)号：US06906959B2
公开(公告)日：2005-06-14
申请号：US10306252
申请日：2002-11-27
申请人： Mark W. Randolph , Chi Chang , Yi He , Wei Zheng , Edward F. Runnion , Zhizheng Liu
发明人： Mark W. Randolph , Chi Chang , Yi He , Wei Zheng , Edward F. Runnion , Zhizheng Liu
IPC分类号： G11C16/04 , G11C16/14 , H01L21/336 , H01L29/792
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/14 , H01L29/7923
摘要： The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well is formed in a semiconductor substrate. A plurality of N-type impurity concentrations are formed in the isolated P-well and a nitride memory cell is fabricated between two of the N-type impurity concentrations. Finally, an electrical contact is coupled to the isolated P-well.
摘要翻译：本发明是一种擦除氮化物存储器件的方法和系统。在本发明的一个实施例中，在半导体衬底中形成隔离的P阱。在分离的P阱中形成多个N型杂质浓度，并且在两种N型杂质浓度之间制造氮化物存储单元。最后，电接点耦合到隔离的P阱。

5. 发明授权

US07995386B2 Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb 有权
标题翻译：将负栅极电压施加到与读取或验证相关的字线附近的字线，以减少相邻的字线干扰
公开(公告)号：US07995386B2
公开(公告)日：2011-08-09
申请号：US12275663
申请日：2008-11-21
申请人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
发明人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/08 , G11C16/3427
摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.
摘要翻译：提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

6. 发明授权

US06795357B1 Method for reading a non-volatile memory cell 失效
标题翻译：读取非易失性存储单元的方法
公开(公告)号：US06795357B1
公开(公告)日：2004-09-21
申请号：US10283590
申请日：2002-10-30
申请人： Zhizheng Liu , Yi He , Mark W. Randolph , Sameer S. Haddad
发明人： Zhizheng Liu , Yi He , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C700
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/26
摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a source voltage to a first bit line that is the source of the selected memory cell and applying a drain voltage to a second bit line that forms a drain junction with the channel region. The source voltage may be a small positive voltage and the drain voltage may be greater than the source voltage. A read voltage is applied to a selected one of the word lines that forms a gate over the charge storage region and a bias voltage is applied to non-selected word lines in the array. The bias voltage may be a negative voltage.
摘要翻译：检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括将源电压施加到作为所选存储单元的源的第一位线并施加到与沟道区形成漏极结的第二位线的漏极电压。源极电压可以是小的正电压，并且漏极电压可能大于源极电压。将读取电压施加到在电荷存储区域上形成栅极的所选择的一条字线，并且将偏置电压施加到阵列中的未选择的字线。偏置电压可以是负电压。

7. 发明授权

US06788583B2 Pre-charge method for reading a non-volatile memory cell 失效
标题翻译：用于读取非易失性存储单元的预充电方法
公开(公告)号：US06788583B2
公开(公告)日：2004-09-07
申请号：US10307749
申请日：2002-12-02
申请人： Yi He , Edward F. Runnion , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Pauling Chen , Binh Le
发明人： Yi He , Edward F. Runnion , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Pauling Chen , Binh Le
IPC分类号： G11C1606
CPC分类号： G11C7/12 , G11C16/0475 , G11C16/24
摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.
摘要翻译：一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域线。将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

8. 发明授权

US06477083B1 Select transistor architecture for a virtual ground non-volatile memory cell array 失效
标题翻译：选择用于虚拟地面非易失性存储单元阵列的晶体管架构
公开(公告)号：US06477083B1
公开(公告)日：2002-11-05
申请号：US09686685
申请日：2000-10-11
申请人： Richard M. Fastow , Mark W. Randolph , Shane C. Hollmer
发明人： Richard M. Fastow , Mark W. Randolph , Shane C. Hollmer
IPC分类号： G11C1604
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , G11C16/14 , H01L27/115
摘要： A bit line selector for a virtual ground non-volatile read only memory (“NROM”) cell array is disclosed. The selector transistors are oriented such that the channel length is perpendicular to the bit line and the channel width is parallel to the bit line. Subsequent reduction in the bit line pitch does not affect the channel width of the select transistors or their drive current.
摘要翻译：公开了用于虚拟非易失性只读存储器（“NROM”）单元阵列的位线选择器。选择器晶体管被定向成使得沟道长度垂直于位线并且沟道宽度平行于位线。位线间距的随后减小不会影响选择晶体管的沟道宽度或其驱动电流。

9. 发明授权

US07125763B1 Silicided buried bitline process for a non-volatile memory cell 失效
标题翻译：非易失性存储单元的硅化掩埋位线工艺
公开(公告)号：US07125763B1
公开(公告)日：2006-10-24
申请号：US09885426
申请日：2001-06-19
申请人： Daniel Sobek , Timothy J. Thurgate , Mark W. Randolph
发明人： Daniel Sobek , Timothy J. Thurgate , Mark W. Randolph
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： A process of fabricating a memory cell that includes a substrate that has a first region and a second region with a channel therebetween by forming a gate above the channel of the substrate, forming a bitline and siliciding the bitline.
摘要翻译：一种制造存储单元的方法，该存储单元包括具有第一区域和第二区域的衬底，所述第一区域和第二区域之间具有通道，通过在衬底的沟道上形成栅极，形成位线并硅化位线。

10. 发明授权

US06897110B1 Method of protecting a memory array from charge damage during fabrication 有权
标题翻译：在制造期间保护存储器阵列免受电荷损伤的方法
公开(公告)号：US06897110B1
公开(公告)日：2005-05-24
申请号：US10305750
申请日：2002-11-26
申请人： Yi He , Wei Zheng , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Ken Tanpairoj
发明人： Yi He , Wei Zheng , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Ken Tanpairoj
IPC分类号： H01L21/336 , H01L21/4763 , H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.
摘要翻译：一种制造存储器阵列的方法，同时保护其免受电荷损坏。可以在衬底中形成可能具有存储器单元的源极/漏极区的位线。字线形成在位线之上，并且可以具有栅极区域。接下来，在位线之上形成耦合到位线之一的第一金属区域。形成不与第一金属区电耦合的第二金属区域。然后，第一金属区域电耦合到第二金属区域。通过保持第一金属区域和位线之间的天线比率降低来减少电荷损坏。为了进一步的保护，还可以在衬底和耦合到位线的金属区域的部分之间形成二极管或保险丝。此外，可以在位线和字线之间形成保险丝，以保护字线。

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