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1. 发明授权

US06681345B1 Field protection against thread loss in a multithreaded computer processor 失效
标题翻译：在多线程计算机处理器中防止线程丢失的现场保护
公开(公告)号：US06681345B1
公开(公告)日：2004-01-20
申请号：US09639190
申请日：2000-08-15
申请人： Salvatore N. Storino , Gregory J. Uhlmann
发明人： Salvatore N. Storino , Gregory J. Uhlmann
IPC分类号： G06F1100
CPC分类号： G06F9/3851 , G06F9/3861
摘要： A method, apparatus, and a program product to protect against thread loss in a multithreaded computer processor. The processor may experience the failure of one or more threads; in accordance with the invention, a functional test can be run to determine which thread is experiencing the failure. If the thread failure results the failure of a register/array that is uniquely associated with the thread, then the invention will disable access to those register/arrays. Each thread may have its own set of register/arrays or it may be uniquely assigned to one of a plurality of storage elements in a multithreaded register/array. Using this invention, a processor may continue processing other threads and the instructions and data associated with the disabled or defective thread can be rerouted.
摘要翻译：一种在多线程计算机处理器中防止线程丢失的方法，装置和程序产品。处理器可能会遇到一个或多个线程的故障; 根据本发明，可以运行功能测试来确定哪个线程正在经历故障。如果线程失败导致与线程唯一相关联的寄存器/阵列的故障，则本发明将禁用对这些寄存器/阵列的访问。每个线程可以具有其自己的一组寄存器/阵列，或者它可以被唯一地分配给多线程寄存器/阵列中的多个存储元件之一。使用本发明，处理器可以继续处理其他线程，并且可以重新路由与禁用或有缺陷的线程相关联的指令和数据。

2. 发明授权

US06748556B1 Changing the thread capacity of a multithreaded computer processor 失效
标题翻译：更改多线程计算机处理器的线程容量
公开(公告)号：US06748556B1
公开(公告)日：2004-06-08
申请号：US09638577
申请日：2000-08-15
申请人： Salvatore N. Storino , Gregory J. Uhlmann
发明人： Salvatore N. Storino , Gregory J. Uhlmann
IPC分类号： G06F1100
CPC分类号： G11C29/26 , G06F9/3851 , G06F9/3861 , G11C8/16 , G11C29/44 , G11C29/818 , G11C29/88 , G11C2029/0401
摘要： In a multithreaded processor, a method and an apparatus to selectively disable one or more threads is disclosed. As multithreading is increasingly becoming the normative paradigm of computer architecture, there still may instances which warrant disabling a thread, such as using operating systems not coded for the specific number of threads, having defective registers/arrays peculiar to a thread, certain kinds of testing procedures. Thus a method is disclosed to test the function of each thread separately and discern if any threads have defective register/arrays. If so or for other reasons, a method and apparatus are disclosed to selectively disable access to the registers/arrays peculiar to the thread. Features of the invention allow the disablement of individual storage elements in multithreaded registers/arrays or to disable access to hardware registers or individual bits in hardware registers associated with the failed thread. Techniques can be used to route data and instructions for the disabled thread to other threads. Preferably, the tests are performed and the method to disable access to the register/arrays are accomplished before the processors are sold.
摘要翻译：在多线程处理器中，公开了一种选择性地禁用一个或多个线程的方法和装置。随着多线程越来越成为计算机体系结构的规范范例，仍然有可能需要禁用线程的情况，例如使用不针对特定线程编码的操作系统，具有线程特有的缺陷寄存器/阵列，某些类型的测试程序。因此，公开了分别测试每个线程的功能的方法，并且辨别任何线程是否具有缺陷寄存器/阵列。如果是这样或由于其他原因，公开了一种方法和装置，以选择性地禁止对线程特有的寄存器/阵列的访问。本发明的特征允许在多线程寄存器/阵列中禁用各个存储元件，或禁止对与故障线程相关联的硬件寄存器中的硬件寄存器或各个位的访问。技术可用于将禁用的线程的数据和指令路由到其他线程。优选地，执行测试，并且在销售处理器之前完成禁止访问寄存器/阵列的方法。

3. 发明申请

US20140003120A1 STATE SENSING SYSTEM FOR EFUSE MEMORY 有权
标题翻译：用于EFUSE存储器的状态感测系统
公开(公告)号：US20140003120A1
公开(公告)日：2014-01-02
申请号：US13535802
申请日：2012-06-28
申请人： Chihhung Liao , Phu Nguyen , Vimal R. Patel , George F. Paulik , Peder J. Paulson , Brian J. Reed , Salvatore N. Storino
发明人： Chihhung Liao , Phu Nguyen , Vimal R. Patel , George F. Paulik , Peder J. Paulson , Brian J. Reed , Salvatore N. Storino
IPC分类号： G11C17/16 , G06F17/50
CPC分类号： G06F17/5027 , G11C7/18 , G11C17/16 , G11C29/027 , G11C2029/4402
摘要： An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.
摘要翻译： eFuse电路可以包括字线，第一eFuse，第一逻辑门，第一blowFET和第一位线放电装置。第一eFuse可以具有耦合到字线的第一端和第二端。第一个eFuse可以在未吹塑时具有第一个阻力，当吹制时可能具有第二个阻力。第一逻辑门可以耦合到第一eFuse的第一端。第一逻辑门可能能够驱动足够的电流来吹动第一eFuse。第一blowFET可以具有耦合到第一电源电压的源极，耦合到编程信号的栅极和耦合到第一eFuse的第二端的漏极。第一位线放电装置可以具有耦合到第一eFuse的第二端的栅极，耦合到第一电源电压的源极和耦合到第一位线的漏极。

4. 发明申请

US20100106996A1 SerDes double rate bitline with interlock to block precharge capture 失效
标题翻译： SerDes双倍位线与互锁以阻止预充电捕获
公开(公告)号：US20100106996A1
公开(公告)日：2010-04-29
申请号：US12260376
申请日：2008-10-29
申请人： Leland Chang , Gary Ditlow , Robert K. Montoye , Salvatore N. Storino
发明人： Leland Chang , Gary Ditlow , Robert K. Montoye , Salvatore N. Storino
IPC分类号： G06F1/06
CPC分类号： H03M9/00 , H03K5/135
摘要： An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened
摘要翻译：本发明的实施例提供了一种将早期时钟脉冲和后期时钟脉冲分离成两个不同锁存器的方法，其中通过位线产生早期时钟脉冲。响应于早期时钟脉冲上升，第一数据波形被发送到第四数据波形。响应于第三数据波形上升，早期预充电被关闭。响应于早期预充电的关闭并且响应于第五数据波形下降，如果第一数据波形具有值1，则第八数据波形上升。响应于第六数据波形上升，第一脉冲锁存器是开了

5. 发明授权

US06808998B2 Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits 失效
标题翻译：消除绝缘体上硅（SOI）动态逻辑电路中寄生双极作用的方法
公开(公告)号：US06808998B2
公开(公告)日：2004-10-26
申请号：US09751163
申请日：2000-12-29
申请人： Salvatore N. Storino , Andrew Douglas Davies
发明人： Salvatore N. Storino , Andrew Douglas Davies
IPC分类号： H01L21331
CPC分类号： H01L27/0266
摘要： The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.
摘要翻译：本发明是一种用于消除绝缘体上硅（SOI）金属氧化物半导体（MOS）器件中的寄生双极晶体管作用的装置和方法。根据本发明，提供耦合到所述SOI电子器件的SOI电子器件和有源放电器件以去激活寄生双极晶体管。通过控制有源放电装置的导通来使寄生双极晶体管的动作失效，所述有源放电装置耦合到所述SOI装置。

6. 发明授权

US06278157B1 Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements 失效
标题翻译：用于消除包括互补氧化物半导体（CMOS）绝缘体上硅（SOI）元件的逻辑电路中的寄生双极性作用的方法和装置
公开(公告)号：US06278157B1
公开(公告)日：2001-08-21
申请号：US09240991
申请日：1999-01-29
申请人： Jeff Van Tran , Salvatore N. Storino
发明人： Jeff Van Tran , Salvatore N. Storino
IPC分类号： H01L2901
CPC分类号： H03K19/00361 , H01L29/78612
摘要： The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by expanding a stack SOI MOS devices arranged to provide a predetermined logic function. The SOI MOS devices are arranged so as to eliminate electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.
摘要翻译：本发明是通过扩展布置成提供预定逻辑功能的堆叠SOI MOS器件来克服绝缘体上硅（SOI）场效应晶体管（FET）中寄生双极放电的不希望的影响的装置和方法。 SOI MOS器件被布置成消除动态逻辑电路的某些中间节点之间的电连接。因此，消除与所述动态电路的所述堆叠的SOI MOS器件的某些中间节点之间的这种电连接相关联的任何寄生双极性电流泄漏路径。

7. 发明授权

US06266800B1 System and method for eliminating effects of parasitic bipolar transistor action in dynamic logic using setup time determination 失效
标题翻译：使用建立时间确定消除寄生双极晶体管作用在动态逻辑中的影响的系统和方法
公开(公告)号：US06266800B1
公开(公告)日：2001-07-24
申请号：US09239290
申请日：1999-01-29
申请人： Gregory John Uhlmann , Salvatore N. Storino
发明人： Gregory John Uhlmann , Salvatore N. Storino
IPC分类号： G06F1750
CPC分类号： H03K19/0008 , H03K19/01707 , H03K19/0966
摘要： A method and apparatus of eliminating the unwanted effects of parasitic bipolar discharge in dynamic logic circuits including silicon-on-insulator (SOI) field effect transistors (FET) by measuring setup time in a logic partition of a dynamic logic circuit having a precharging device and an output device. The method determines a first time delay of a clock signal from said logic partition to a control input of said precharging device and a second time delay of a logic signal from said logic partition to a control input of said output device. The method then determines a setup time according to said first and second time delays. The precharging device remains active during the setup time to prevent parasitic bipolar discharge.
摘要翻译：一种通过测量具有预充电装置的动态逻辑电路的逻辑分区中的建立时间来消除包括绝缘体上硅（SOI）场效应晶体管（FET）在动态逻辑电路中的有害影响的方法和装置，以及输出设备。该方法确定从所述逻辑分区到所述预充电装置的控制输入的时钟信号的第一时间延迟以及从所述逻辑分区到所述输出装置的控制输入的逻辑信号的第二时间延迟。该方法然后根据所述第一和第二时间延迟确定建立时间。预充电器件在建立时间内保持有效，以防止寄生双极放电。

8. 发明授权

US6150869A Method and apparatus for body control in silicon-on-insulator (SOI) domino circuits 失效
标题翻译：绝缘体上硅（SOI）多米诺骨牌电路中的身体控制方法和装置
公开(公告)号：US6150869A
公开(公告)日：2000-11-21
申请号：US289034
申请日：1999-04-09
申请人： Salvatore N. Storino , Jeff V. Tran , Robert Russell Williams
发明人： Salvatore N. Storino , Jeff V. Tran , Robert Russell Williams
IPC分类号： H03K19/096 , H03K3/01
CPC分类号： H03K19/0963
摘要： Methods and apparatus are provided for body control in silicon-on-insulator (SOI) domino circuits. The silicon-on-insulator (SOI) domino circuit includes a clock input and an input transistor stack including a plurality of input transistors. Each of the plurality of input transistors receives a data input. An intermediate precharge node is connected to the input transistor stack. An output inverter is connected to the intermediate precharge node. The output inverter includes a pair of silicon-on-insulator (SOI) transistors. A clocked transistor is connected to a body of at least one of the pair of silicon-on-insulator (SOI) transistors. The clocked transistor predischarges the body of the SOI transistor. Another clocked transistor is connected between ground and a body of an evaluate transistor connected to the input transistor stack. The body of the evaluate transistor is predischarged by the clocked transistor.
摘要翻译：提供了用于绝缘体上硅（SOI）多米诺骨牌电路中的身体控制的方法和装置。绝缘体上硅（SOI）多米诺骨电路包括时钟输入和包括多个输入晶体管的输入晶体管堆叠。多个输入晶体管中的每一个接收数据输入。中间预充电节点连接到输入晶体管堆叠。输出反相器连接到中间预充电节点。输出反相器包括一对绝缘体上硅（SOI）晶体管。时钟晶体管连接到一对绝缘体上硅（SOI）晶体管中的至少一个的主体。时钟晶体管会牺牲SOI晶体管的体积。另一个时钟晶体管连接在接地和连接到输入晶体管堆叠的评估晶体管的主体之间。评估晶体管的主体由时钟晶体管预充电。

9. 发明授权

US6094072A Methods and apparatus for bipolar elimination in silicon-on-insulator (SOI) domino circuits 有权
标题翻译：绝缘体上硅（SOI）多米诺骨电路中双极消除的方法和装置
公开(公告)号：US6094072A
公开(公告)日：2000-07-25
申请号：US268923
申请日：1999-03-16
申请人： Andrew Douglas Davies , Salvatore N. Storino , Jeff V. Tran , Robert Russell Williams
发明人： Andrew Douglas Davies , Salvatore N. Storino , Jeff V. Tran , Robert Russell Williams
IPC分类号： H01L27/08 , H01L21/8238 , H01L27/092 , H01L29/786 , H03K19/003 , H03K19/094 , H03K19/096 , H03K19/20
CPC分类号： H03K19/00315 , H01L27/0921 , H03K19/094
摘要： In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. Apparatus for bipolar elimination in silcon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor. An input is coupled to the domino silicon-n-insulator (SOI) field effect transistor. A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor. The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit couples the input to the domino silicon-on-insulator (SOI) field effect transistor. The output of the dynamic input circuit is low during the precharge mode. The output of the dynamic input circuit corresponds to the input during the evaluate mode. The output of the dynamic input circuit is used to gate the predischarging device.
摘要翻译：简而言之，提供了用于绝缘体上硅（SOI）多米诺骨电路中的双极消除的方法和装置。在绝缘体上硅（SOI）多米诺骨电路中双极消除的装置包括绝缘体上硅（SOI）场效应晶体管。输入耦合到多米诺硅绝缘体（SOI）场效应晶体管。预充电器件耦合到所述多硅绝缘体（SOI）场效应晶体管。预充电器件在多米诺骨电路的预充电模式下被激活，使得SOI寄生双极晶体管不被激活。动态输入电路将输入耦合到绝缘体上硅（SOI）场效应晶体管。在预充电模式期间，动态输入电路的输出为低电平。动态输入电路的输出对应于评估模式下的输入。动态输入电路的输出用于对预充电设备进行门控。

10. 发明申请

US20080079158A1 METAL FILL REGION OF A SEMICONDUCTOR CHIP 失效
标题翻译：金属填充区半导体芯片
公开(公告)号：US20080079158A1
公开(公告)日：2008-04-03
申请号：US11538118
申请日：2006-10-03
申请人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
发明人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
IPC分类号： H01L23/52
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.
摘要翻译：公开了一种半导体芯片的金属填充区域，其包括半导体芯片的多个层组，每组包括设置在彼此平行的平面中的第一金属填充层，第二金属填充层和绝缘层，设置在每个金属填充层中的多个金属填充片，每个片的金属填充片轴线，其中每个轴与任何参考点垂直地相交于所述金属填充层的平面和绝缘层，以及金属填充图案，被配置为定位所述片，使得所述第一金属填充层中的每个片的轴线在与所述金属填充轴中的每一个垂直的至少一个方向上在所述第二金属填充层中的每个片的轴线线性位移。

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