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1. 发明授权

US06914198B2 Electrical device allowing for increased device densities 失效
标题翻译：电气设备允许增加设备密度
公开(公告)号：US06914198B2
公开(公告)日：2005-07-05
申请号：US10237579
申请日：2002-09-09
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
IPC分类号： H01L23/495 , H05K1/02 , H05K1/09 , H05K3/32 , H05K1/18
CPC分类号： H05K3/4007 , H01L23/4951 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K1/095 , H05K3/321 , H05K3/325 , H05K3/326 , H05K2201/0133 , H05K2201/0314 , H05K2201/0367 , H05K2201/09909 , H05K2201/10454 , H05K2201/10696 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： Disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.
摘要翻译：公开了一种包括具有有源侧和非有源侧的电路的器件，封装电路的有源侧的封装，并且不包围电路的非有源侧的一部分，以及引线，其具有连接到第一端经由引线芯片连接到电路的有源侧，并且具有从封装延伸的第二端。还公开了一种包括由柔性导体形成的电路和引线的器件，其中引线具有连接到电路的第一端。

2. 发明授权

US07084351B2 Electrical device allowing for increased device densities 失效
公开(公告)号：US07084351B2
公开(公告)日：2006-08-01
申请号：US10237645
申请日：2002-09-09
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
IPC分类号： H05K1/18
CPC分类号： H05K3/4007 , H01L23/4951 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K1/095 , H05K3/321 , H05K3/325 , H05K3/326 , H05K2201/0133 , H05K2201/0314 , H05K2201/0367 , H05K2201/09909 , H05K2201/10454 , H05K2201/10696 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.

3. 发明授权

US06535393B2 Electrical device allowing for increased device densities 失效
标题翻译：电气设备允许增加设备密度
公开(公告)号：US06535393B2
公开(公告)日：2003-03-18
申请号：US09205796
申请日：1998-12-04
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
IPC分类号： H05K114
CPC分类号： H05K3/4007 , H01L23/4951 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K1/095 , H05K3/321 , H05K3/325 , H05K3/326 , H05K2201/0133 , H05K2201/0314 , H05K2201/0367 , H05K2201/09909 , H05K2201/10454 , H05K2201/10696 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.
摘要翻译：一种装置，包括电路，具有连接到所述电路并具有第二端的第一端的引线和连接到所述引线的第二端的可变形结构。本发明可以实现在电路板上，使得电路板包括基板和连接到所述基板的可变形结构。还公开了一种包括具有有源侧和非有源侧的电路的装置，封装电路的有源侧的封装件，并且不包围电路的非有源侧的一部分，以及具有第一端通过芯片上引线连接到电路的有源侧，并具有从封装延伸的第二端。还公开了一种包括由柔性导体形成的电路和引线的器件，其中引线具有连接到电路的第一端。

4. 发明授权

US06909055B2 Electrical device allowing for increased device densities 失效
标题翻译：电气设备允许增加设备密度
公开(公告)号：US06909055B2
公开(公告)日：2005-06-21
申请号：US10301990
申请日：2002-11-22
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
IPC分类号： H01L23/495 , H05K1/02 , H05K1/09 , H05K3/32 , H05K1/11
CPC分类号： H05K3/4007 , H01L23/4951 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K1/095 , H05K3/321 , H05K3/325 , H05K3/326 , H05K2201/0133 , H05K2201/0314 , H05K2201/0367 , H05K2201/09909 , H05K2201/10454 , H05K2201/10696 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.
摘要翻译：一种装置，包括电路，具有连接到所述电路并具有第二端的第一端的引线和连接到所述引线的第二端的可变形结构。本发明可以实现在电路板上，使得电路板包括基板和连接到所述基板的可变形结构。

5. 发明授权

US08502353B2 Through-wafer interconnects for photoimager and memory wafers 失效
标题翻译：用于光刻机和存储晶圆的透晶片互连
公开(公告)号：US08502353B2
公开(公告)日：2013-08-06
申请号：US13154550
申请日：2011-06-07
申请人： Salman Akram , Charles M. Watkins , William M. Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
发明人： Salman Akram , Charles M. Watkins , William M. Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
IPC分类号： H01L23/485
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译：公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

6. 发明申请

US20110074043A1 METHOD OF FORMING VIAS IN SEMICONDUCTOR SUBSTRATES AND RESULTING STRUCTURES 有权
标题翻译：在半导体衬底和结构结构中形成VIAS的方法
公开(公告)号：US20110074043A1
公开(公告)日：2011-03-31
申请号：US12955359
申请日：2010-11-29
申请人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
发明人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
IPC分类号： H01L23/48
CPC分类号： H01L21/76898
摘要： Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.
摘要翻译：公开了在半导体衬底中形成贯通孔的方法和所得到的结构。在一个实施例中，可以通过从活性表面通过其上的导电元件和导电元件下面的基底的一部分形成部分通孔来形成通孔。然后可以通过从后表面的激光烧蚀或钻孔来完成通孔。在另一个实施例中，部分通孔可以通过激光烧蚀或从衬底的背面钻孔到其中的预定距离来形成。通孔可以通过形成延伸通过导电元件和下面的衬底以与激光钻孔的部分通孔相交的部分通孔从活性表面完成。在另一个实施例中，可以首先通过激光烧蚀或从衬底的背面进行钻孔形成部分通孔，然后通过干蚀刻来完成通孔。

7. 发明授权

US07713841B2 Methods for thinning semiconductor substrates that employ support structures formed on the substrates 有权
标题翻译：减薄采用在基板上形成的支撑结构的半导体衬底的方法
公开(公告)号：US07713841B2
公开(公告)日：2010-05-11
申请号：US10666742
申请日：2003-09-19
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree , Sidney B. Rigg , William M. Hiatt , Peter Benson , Kyle K. Kirby , Salman Akram
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree , Sidney B. Rigg , William M. Hiatt , Peter Benson , Kyle K. Kirby , Salman Akram
IPC分类号： H01L21/46
CPC分类号： G03F7/0037 , B33Y30/00 , B33Y70/00 , B33Y80/00 , G03F7/0047
摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface. Assemblies that include the support structure and a semiconductor substrate are also within the scope of the present invention, as are methods for forming the support structures and thinning and post-thinning processes that include use of the support structures.
摘要翻译：在半导体衬底的薄化或后研磨以及后稀化处理期间与半导体衬底一起使用的支撑结构包括基本上沿半导体衬底的外周延伸并且围绕半导体衬底的外周延伸的部分，以使薄化半导体基板具有刚性。支撑结构可以被配置为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。包括支撑结构和半导体衬底的组件也在本发明的范围内，形成支撑结构的方法和包括使用支撑结构的减薄和后变薄工艺也是如此。

8. 发明授权

US07504615B2 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers 有权
标题翻译：具有光学器件的微电子成像器和制造这种微电子成像器的方法
公开(公告)号：US07504615B2
公开(公告)日：2009-03-17
申请号：US11727545
申请日：2007-03-27
申请人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
发明人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
IPC分类号： H01L27/00 , H01L31/0232
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.
摘要翻译：微电子成像器组件包括包括衬底的工件和在衬底上和/或衬底中的多个成像管芯。基板包括前侧和后侧，并且成像管芯包括在基板的前侧的成像传感器和可操作地耦合到图像传感器的外部触点。微电子成像器组件还包括相对于成像管芯叠加的光学支架。光学支撑件可以直接在基板上或衬底上的盖上。单个光学支撑件可以具有（a）与图像传感器中的一个对准的开口，以及（b）与图像传感器相距一定距离处的轴承元件。微电子成像器组件还可以包括由光学器件支撑件安装或以其它方式承载的光学器件。

9. 发明授权

US07419841B2 Microelectronic imagers and methods of packaging microelectronic imagers 有权
标题翻译：微电子成像器和包装微电子成像器的方法
公开(公告)号：US07419841B2
公开(公告)日：2008-09-02
申请号：US11494453
申请日：2006-07-28
申请人： Warren M. Farnworth , Sidney B. Rigg , William M. Hiatt , Kyle K. Kirby , Peter A. Benson , James M. Wark , Alan G. Wood , David R. Hembree , Salman Akram , Charles M. Watkins
发明人： Warren M. Farnworth , Sidney B. Rigg , William M. Hiatt , Kyle K. Kirby , Peter A. Benson , James M. Wark , Alan G. Wood , David R. Hembree , Salman Akram , Charles M. Watkins
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , H01L23/481 , H01L24/48 , H01L31/0203 , H01L31/02325 , H01L2224/48227 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.
摘要翻译：本文公开了微电子成像器和用于封装微电子成像器的方法。在一个实施例中，微电子成像单元可以包括微电子管芯，图像传感器，电耦合到图像传感器的集成电路以及电耦合到集成电路的接合焊盘。导电晶片互连延伸穿过管芯并且与焊盘接触。互连可以包括完全延伸穿过基底的通道和具有至少部分地设置在通道中的导电填充材料的接合垫。导电支撑构件由接合垫承载和突出。图像传感器上的盖连接到支撑构件。

10. 发明授权

US07214962B2 Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer 失效
标题翻译：使用各向异性导电层测试和组装凸起装置的装置和方法
公开(公告)号：US07214962B2
公开(公告)日：2007-05-08
申请号：US11083057
申请日：2005-03-16
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L23/13 , G01R1/0466 , G01R1/0483 , H01L23/49827 , H01L2224/05571 , H01L2224/05573 , H01L2224/131 , H01L2224/16237 , H01L2224/8114 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/15174 , H05K3/325 , H05K3/326 , H01L2224/05599
摘要： The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads. In another embodiment, an apparatus for testing a bumped device having a plurality of conductive bumps includes a substrate having a plurality of contact pads distributed thereon and substantially alignable with the plurality of conductive bumps, and an anisotropically conductive layer disposed on the first surface and engageable with the plurality of conductive bumps to electrically couple each of the conductive bumps with a corresponding one of the contact pads. Alternately, the test apparatus may also include an alignment device or a bumped device handler. In another embodiment, a method of testing a bumped device includes engaging a plurality of contact pads with an anisotropically conductive layer, engaging the plurality of conductive bumps with the anisotropically conductive layer substantially opposite from and in approximate alignment with the plurality of contact pads, forming a plurality of conductive paths through the anisotropically conductive layer so that each of the conductive bumps is electrically coupled to one of the contact pads, and applying test signals through at least some of the contact pads and the conductive paths to at least some of the conductive bumps.
摘要翻译：本发明涉及使用各向异性导电层测试和组装凸模和凸起装置的装置和方法。在一个实施例中，半导体器件包括具有形成在其上的多个导电凸起的凸起器件，衬底，其上分布有多个接触焊盘并且与多个导电凸块大致对准，并且各向异性导电层设置在机械耦合到凸起的装置和衬底。各向异性导电层将每个导电凸块与对应的一个接触垫电耦合。在另一个实施例中，一种用于测试具有多个导电凸块的凸起器件的设备包括：衬底，其具有分布在其上的多个接触焊盘并且可与多个导电凸块基本对准，以及设置在第一表面上并可接合的各向异性导电层其中多个导电凸块将每个导电凸块与相应的一个接触垫电耦合。或者，测试装置还可以包括对准装置或凸起的装置处理器。在另一个实施例中，一种测试凸起装置的方法包括：将多个接触垫与各向异性导电层接合，使多个导电凸块与多个接触垫基本上相对并与其大致对准的各向异性导电层接合，形成通过各向异性导电层的多个导电路径，使得每个导电凸块电耦合到一个接触焊盘，以及将测试信号通过至少一些接触焊盘和导电路径施加到至少一些导电颠簸

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