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1. 发明授权

US07217950B2 Insulated gate tunnel-injection device having heterojunction and method for manufacturing the same 有权
标题翻译：具有异质结的绝缘栅隧道注入装置及其制造方法
公开(公告)号：US07217950B2
公开(公告)日：2007-05-15
申请号：US10682154
申请日：2003-10-10
申请人： Saichirou Kaneko , Masakatsu Hoshi , Kraisorn Throngnumchai , Tetsuya Hayashi , Hideaki Tanaka , Teruyoshi Mihara
发明人： Saichirou Kaneko , Masakatsu Hoshi , Kraisorn Throngnumchai , Tetsuya Hayashi , Hideaki Tanaka , Teruyoshi Mihara
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0653 , H01L29/0878 , H01L29/1602 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7813 , H01L29/7828
摘要： The present invention-provides a tunnel-injection device which encompasses, a reception layer made of a first semiconductor, a barrier-forming layer made of a second semiconductor having a bandgap-narrower than the first semiconductor, being in metallurgical contact with the reception layer, a gate insulating film disposed on the barrier-forming layer. The gate electrode controls the width of the barrier generated at the heterojunction interface between the reception layer and the barrier-forming layer so as to change the tunneling probability of carriers through the barrier. The device further encompasses a carrier receiving region being contact with the reception layer and a carrier-supplying region being contact with the barrier-forming layer.
摘要翻译：本发明提供了一种隧道注入装置，其包括由第一半导体制成的接收层，由具有窄于第一半导体带隙的第二半导体制成的阻挡层形成层与接收层冶金接触设置在阻挡层形成层上的栅极绝缘膜。栅电极控制在接收层和阻挡层形成层之间的异质结界面处产生的势垒的宽度，以便改变载流子穿过屏障的隧穿概率。该装置还包括与接收层接触的载体接收区域和与阻挡层形成层接触的载体供给区域。

2. 发明授权

US07183575B2 High reverse voltage silicon carbide diode and method of manufacturing the same high reverse voltage silicon carbide diode 有权
标题翻译：高反向电压碳化硅二极管和制造相同高反向碳化硅二极管的方法
公开(公告)号：US07183575B2
公开(公告)日：2007-02-27
申请号：US10368016
申请日：2003-02-19
申请人： Yoshio Shimoida , Saichirou Kaneko , Hideaki Tanaka , Masakatsu Hoshi , Kraisom Throngnumchai , Teruyoshi Mihara , Tetsuya Hayashi
发明人： Yoshio Shimoida , Saichirou Kaneko , Hideaki Tanaka , Masakatsu Hoshi , Kraisom Throngnumchai , Teruyoshi Mihara , Tetsuya Hayashi
IPC分类号： H01L29/15
CPC分类号： H01L29/267 , H01L29/1608 , H01L29/861
摘要： A high reverse voltage diode includes a hetero junction made up from a silicon carbide base layer, which constitutes a first semiconductor base layer, and a polycrystalline silicon layer, which constitutes a second semiconductor layer, and whose band gap is different from that of the silicon carbide base layer. A low concentration N type polycrystalline silicon layer is deposited on a first main surface side of the silicon carbide base layer, and a metal electrode is formed on a second main surface side of the silicon carbide base layer which is opposite to the first main surface side thereof.
摘要翻译：高反向电压二极管包括由构成第一半导体基底层的碳化硅基底层和构成第二半导体层的多晶硅层构成的异质结，并且其带隙与硅的带隙不同碳化物基层。在碳化硅基底层的第一主表面侧沉积低浓度N型多晶硅层，在与第一主表面侧相反的碳化硅基底层的第二主表面侧上形成金属电极其中。

3. 发明授权

US5675169A Motor driving circuit with surge detection/protection and its structure in a semiconductor device 失效
标题翻译：具有浪涌检测/保护的电机驱动电路及其在半导体器件中的结构
公开(公告)号：US5675169A
公开(公告)日：1997-10-07
申请号：US451750
申请日：1995-05-26
申请人： Masakatsu Hoshi , Teruyoshi Mihara , Kraisorn Throngnumchai
发明人： Masakatsu Hoshi , Teruyoshi Mihara , Kraisorn Throngnumchai
IPC分类号： H02P7/29 , H01L27/02 , H02P7/00 , H03K17/082 , H03K17/687 , H03K17/695 , H01L23/62 , H01L29/76 , H01L29/94 , H02H5/04
CPC分类号： H01L27/0251 , H02P7/04 , H03K17/0822 , H03K17/6871 , H01L2924/0002
摘要： A semiconductor device having a surge input detecting circuit is provided with the driving circuit for, for example, reversible motor. To prevent MOS power transistors constituting the power driving circuit from their destructive breakdowns (failures), when the surge input detecting circuit block detects the surge voltage input through the driving circuit which exceeds a predetermined voltage, namely, a maximum rated power supply voltage of the power driving circuit, the surge input detecting circuit outputs the signal to turn the MOS power transistors in off-states. These circuit elements are integrally mounted on a semiconductor chip. The surge input detecting circuit block detects such a surge input through a power supply terminal in terms of either of its voltage, its current, or the temperature rise in the semiconductor chip. The breakdown voltage per power transistor can be half the maximum rated power supply voltage. In addition, the surge input detecting circuit block and these power MOS transistors are fabricated into the same semiconductor chip.
摘要翻译：具有浪涌输入检测电路的半导体器件设置有用于例如可逆电动机的驱动电路。为了防止构成电力驱动电路的MOS功率晶体管的破坏性故障（故障），当浪涌输入检测电路块检测到通过驱动电路输入的浪涌电压超过预定电压时，即最大额定电源电压电源驱动电路，浪涌输入检测电路输出该信号，使MOS功率晶体管处于断开状态。这些电路元件一体地安装在半导体芯片上。浪涌输入检测电路块根据其电压，电流或半导体芯片的温度升高来检测通过电源端子的浪涌输入。每个功率晶体管的击穿电压可以是最大额定电源电压的一半。此外，浪涌输入检测电路块和这些功率MOS晶体管被制造成相同的半导体芯片。

4. 发明授权

US5629704A Target position detecting apparatus and method utilizing radar 失效
标题翻译：目标位置检测装置及利用雷达的方法
公开(公告)号：US5629704A
公开(公告)日：1997-05-13
申请号：US527677
申请日：1995-09-12
申请人： Kraisorn Throngnumchai , Teruyoshi Mihara , Hiroshige Fukuhara , Yukitsugu Hirota
发明人： Kraisorn Throngnumchai , Teruyoshi Mihara , Hiroshige Fukuhara , Yukitsugu Hirota
IPC分类号： H01L31/10 , G01S7/02 , G01S7/48 , G01S7/523 , G01S13/10 , G01S13/46 , G01S13/93 , G01S15/10 , G01S15/46 , G01S15/93 , G01S17/10 , G01S17/46 , G01S17/93 , H01L31/00 , G01S7/483
CPC分类号： G01S17/46 , G01S7/4914 , G01S13/46 , G01S15/46
摘要： In a radar target position detecting apparatus, beams (, for example, light beams) irradiated from a transmitter(, for example, LED) have a predetermined divergence angle, a plurality of light (beam) receiving elements such as photodiode arrays each having a different receiving angle (directivity) are arranged in an array form, and a direction of a reflected wave (beam) is identified according to a position of the arrayed beam (wave) receiving elements in the array at which the reflected wave (beam) is captured.
摘要翻译：在雷达目标位置检测装置中，从发射器（例如，LED）照射的光束（例如，光束）具有预定的发散角，多个光（光束）接收元件，例如光电二极管阵列，每个具有以阵列形式布置不同的接收角（方向性），并且根据反射波（波束）的阵列中的阵列波束（波）接收元件的位置来识别反射波（波束）的方向被捕获。

5. 发明授权

US5635742A Lateral double-diffused mosfet 失效
标题翻译：侧向双扩散mosfet
公开(公告)号：US5635742A
公开(公告)日：1997-06-03
申请号：US660211
申请日：1996-06-03
申请人： Masakatsu Hoshi , Teruyoshi Mihara
发明人： Masakatsu Hoshi , Teruyoshi Mihara
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/06 , H01L29/417 , H01L29/45 , H01L29/78 , H01L27/10
CPC分类号： H01L29/0696 , H01L29/41741 , H01L29/7809 , H01L29/41766 , H01L29/456
摘要： A lateral double-diffused MOSFET has a semiconductor substrate, a drain region formed on the substrate, a gate insulation film formed on the drain region, a gate electrode formed on the gate insulation film, source and drain openings formed through the gate electrode, a first conductive region formed under the drain region, a source electrode formed on the source openings, a drain electrode formed on the drain openings, and second conductive regions for connecting the drain electrode to the first conductive region. The source and drain openings are cyclically arranged so that at least two rows of source openings are arranged between adjacent drain openings, to reduce the ON resistance of the MOSFET.
摘要翻译：横向双扩散MOSFET具有半导体基板，形成在基板上的漏极区域，形成在漏极区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，通过栅电极形成的源极和漏极开口，形成在漏极区域下方的第一导电区域，形成在源极开口上的源极电极，形成在漏极开口上的漏电极，以及用于将漏电极连接到第一导电区域的第二导电区域。源极和漏极开口循环布置，使得至少两排源极开口布置在相邻的漏极开口之间，以降低MOSFET的导通电阻。

6. 发明授权

US5184204A Semiconductor device with high surge endurance 失效
标题翻译：具有高浪涌耐久性的半导体器件
公开(公告)号：US5184204A
公开(公告)日：1993-02-02
申请号：US645872
申请日：1991-01-24
申请人： Teruyoshi Mihara , Tsutomu Matsushita , Kenji Yao , Masakatsu Hoshi , Yutaka Enokido , Yukitsugu Hirota
发明人： Teruyoshi Mihara , Tsutomu Matsushita , Kenji Yao , Masakatsu Hoshi , Yutaka Enokido , Yukitsugu Hirota
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7808 , H01L29/0619 , H01L29/0626 , H01L29/0696 , H01L29/1095 , H01L29/0878
摘要： A semiconductor device in which the breakdown voltages of the cell unit and the guard ring can easily be matched, and the surge endurance of the device can be improved. This semiconductor device includes a guard ring region surrounding the cell diffusion layers which is formed from an array of a plurality of guard ring cells, where each of the guard ring cells is identical to each of the cell diffusion layers and the guard ring cells are electrically connected mutually, so that the diffusion depths of each of the cells of the guard ring region and the cell diffusion layers are identical, and consequently the breakdown voltages for the guard ring region and the cell diffusion layers can be made equal to each other.
摘要翻译：可以容易地匹配电池单元和保护环的击穿电压的半导体器件，并且可以提高器件的浪涌耐久性。该半导体器件包括围绕由多个保护环电池的阵列形成的电池扩散层的保护环区域，其中每个保护环电池与每个电池扩散层相同，保护环电池为电相互连接，使得保护环区域和电池扩散层的每个电池的扩散深度相同，因此保护环区域和电池扩散层的击穿电压可以彼此相等。

7. 发明授权

US5682048A Groove-type semiconductor device 失效
标题翻译：槽型半导体器件
公开(公告)号：US5682048A
公开(公告)日：1997-10-28
申请号：US648965
申请日：1996-05-17
申请人： Toshiro Shinohara , Masakatsu Hoshi , Teruyoshi Mihara
发明人： Toshiro Shinohara , Masakatsu Hoshi , Teruyoshi Mihara
IPC分类号： H01L21/768 , H01L21/336 , H01L23/522 , H01L29/06 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7809 , H01L29/0696 , H01L29/4238 , H01L2924/0002
摘要： A semiconductor structure having a plurality of drivers in and on the same semiconductor substrate is arranged to increase the density of integrated components and reduce the on resistance. The semiconductor structure employs a double layer interconnection structure having source and drain electrodes at two different levels, and an insulated gate electrode in a groove formed the semiconductor substrate. Each drain lead region having a low resistivity material extends from the upper surface of the substrate to a low resistivity buried layer. Each drain opening is surrounded by a source zone formed with a series of source holes or a long and narrow source slot, and this basic pattern is regularly repeated in a plane.
摘要翻译：布置具有在同一半导体衬底中的多个驱动器的半导体结构以增加集成部件的密度并降低导通电阻。半导体结构采用具有两个不同电平的源极和漏极的双层互连结构，并且在形成半导体衬底的沟槽中形成绝缘栅电极。具有低电阻率材料的每个漏极引线区域从衬底的上表面延伸到低电阻率掩埋层。每个排水开口由形成有一系列源孔或长而窄的源槽的源区围绕，并且该基本图案在平面中有规律地重复。

8. 发明授权

US5192989A Lateral DMOS FET device with reduced on resistance 失效
标题翻译：具有降低耐电压性能的侧面DMOS FET器件
公开(公告)号：US5192989A
公开(公告)日：1993-03-09
申请号：US618358
申请日：1990-11-27
申请人： Tsutomu Matsushita , Teruyoshi Mihara , Masakatsu Hoshi , Kenji Yao
发明人： Tsutomu Matsushita , Teruyoshi Mihara , Masakatsu Hoshi , Kenji Yao
IPC分类号： H01L29/06 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/7801 , H01L29/0696 , H01L29/41758
摘要： A lateral DMOS FET device which has a small on resistance. The device includes a cell structure formed by a plurality of unit cells, each unit cell including: a source region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the source region; and a plurality of drain contact regions of first conduction type located around the channel region; and a source electrode, a gate electrode, and a drain electrode, all of which are formed on the same one side of the substrate. Alternatively, each unit cell may includes: a drain contact region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the drain contact region; and a plurality of source regions of first conduction type located around the channel region.
摘要翻译：具有导通电阻小的横向DMOS FET器件。该装置包括由多个单元电池形成的单元结构，每个单位单元包括：形成在第一导电类型的基板的一侧的第一导电类型的源区; 形成在源极区周围的第二导电类型的沟道区; 以及位于所述沟道区周围的多个第一导电类型的漏极接触区域; 以及源电极，栅极电极和漏电极，所有这些都形成在基板的相同的一侧上。或者，每个单电池可以包括：形成在第一导电类型的衬底的一侧上的第一导电类型的漏极接触区域; 形成在所述漏极接触区域周围的第二导电类型的沟道区域; 以及位于沟道区周围的多个第一导电类型的源极区。

9. 再颁专利

USRE35405E Method of manufacturing semiconductor device utilizing an accumulation layer 失效
标题翻译：利用蓄积层制造半导体器件的方法
公开(公告)号：USRE35405E
公开(公告)日：1996-12-17
申请号：US288731
申请日：1994-08-12
申请人： Yoshinori Murakami , Teruyoshi Mihara
发明人： Yoshinori Murakami , Teruyoshi Mihara
IPC分类号： H01L21/335 , H01L21/336 , H01L29/423 , H01L29/772 , H01L29/78 , H01L21/338
CPC分类号： H01L29/66416 , H01L29/66666 , H01L29/7722 , H01L29/7827 , H01L29/4232 , H01L29/4238 , Y10S148/05
摘要： A method of manufacturing semiconductor devices by forming a U-shaped insulated gate on a substrate, etching the substrate to expose a sidewall of the U-shaped insulated gate, covering the exposed part with a masking material, forming the sidewall of the masking material only adjoining to the exposed U-shaped insulated gate, etching the substrate vertically to form a groove, forming a semiconductor region on the groove and burying a metal into the groove.
摘要翻译：一种通过在衬底上形成U形绝缘栅来制造半导体器件的方法，蚀刻衬底以露出U形绝缘栅极的侧壁，用掩模材料覆盖暴露部分，仅形成掩模材料的侧壁邻接于暴露的U形绝缘栅极，垂直蚀刻衬底以形成沟槽，在沟槽上形成半导体区域并将金属埋入槽中。

10. 发明授权

US4931846A Vertical MOSFET having voltage regulator diode at shallower subsurface position 失效
标题翻译：垂直MOSFET在较浅的地下位置具有稳压二极管
公开(公告)号：US4931846A
公开(公告)日：1990-06-05
申请号：US185387
申请日：1988-04-25
申请人： Teruyoshi Mihara
发明人： Teruyoshi Mihara
IPC分类号： H01L27/02 , H01L27/07 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7808 , H01L27/0255 , H01L27/0727 , H01L29/1095 , H01L29/0626 , H01L29/0878
摘要： A vertical MOSFET device has a first conductivity type substrate layer serving as a drain, a second conductivity type channel region extending into said substrate layer from a top surface, and a first conductivity type source region extending into the channel region from the top surface. The channel region has a peripheral subregion extending deeply into the substrate layer from the top surface under an insulated gate electrode, and a shallow central subregion shallower than the peripheral subregion. There is further provided a second conductivity type underlying layer formed under the shallow central subregion so as to form a voltage regulating diode with the channel region at a position shallower than the bottom of the peripheral subregion.

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