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1. 发明专利

DE69617391T2 未知
公开(公告)号：DE69617391T2
公开(公告)日：2002-07-11
申请号：DE69617391
申请日：1996-07-03
申请人： SHARP KK
发明人： SUMINAGA YASUO , KOMATSU KOJI
IPC分类号： G11C11/41 , G11C7/18 , G11C17/12 , G11C17/18 , G11C7/00
摘要： In a semiconductor storage device, a potential corresponding to a position of a word line selected from the memory cell array is applied to a bank selection line which is connected to the gate of a bank selection transistor, as an ON potential for the bank selection transistor so that it is possible to reduce the variation in the bit line potential depending upon the position of a memory cell in a bank of a ROM using a bank system.

2. 发明专利

DE69617391D1 未知
公开(公告)号：DE69617391D1
公开(公告)日：2002-01-10
申请号：DE69617391
申请日：1996-07-03
申请人： SHARP KK
发明人： SUMINAGA YASUO , KOMATSU KOJI
IPC分类号： G11C11/41 , G11C7/18 , G11C17/12 , G11C17/18 , G11C7/00
摘要： In a semiconductor storage device, a potential corresponding to a position of a word line selected from the memory cell array is applied to a bank selection line which is connected to the gate of a bank selection transistor, as an ON potential for the bank selection transistor so that it is possible to reduce the variation in the bit line potential depending upon the position of a memory cell in a bank of a ROM using a bank system.

3. 发明专利

JPH11238813A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH11238813A
公开(公告)日：1999-08-31
申请号：JP33479798
申请日：1998-11-25
申请人： SHARP KK
发明人： KOMATSU KOJI
IPC分类号： G11C7/18 , G11C8/12 , G11C11/401 , G11C11/41 , G11C17/12 , H01L21/8246 , H01L27/112
摘要： PROBLEM TO BE SOLVED: To improve the access speed of a mask ROM memory cell array that that of a conventional one after an increase in the area of a chip is inhibited by a method wherein main bit lines are travelled across a plurality of bank regions in the column direction and the main bit lines, which correspond to selected blocks in parallel to external bit lines, are connected with the external bit lines. SOLUTION: This mask ROM memory cell array is provided with a plurality of blocks BLK0 to BLKn arranged in the column direction and each block BLK is provided with a plurality of banks BNK0 to BNKm arranged in the column direction. In each bank BNK, memory cells are arranged into the form of matrix. A bank select line BS and a word line WL are selected, whereby one of the memory cells is made to have continuity with main bit lines and main ground lines. External bit lines GB are wired in almost parallel to the main bit lines MB and are connected with the main bit line MB of each block BLK via a block selection transistor TC between blocks.

4. 发明专利

JPH11185490A SENSE AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH11185490A
公开(公告)日：1999-07-09
申请号：JP35470697
申请日：1997-12-24
申请人： SHARP KK
发明人： KOMATSU KOJI
IPC分类号： G11C11/419 , G11C7/06 , G11C11/56 , G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To reduce consumption power without delaying a decision time of a final comparison result by limiting a current of a predetermined or all sense subamplifiers among current mirror type sense subamplifiers. SOLUTION: A drain potential of a gate of an N type MOSFET: QNX constituting a switching element is Vs. The Vs is determined as a balance point of a reference potential VREF and a judgment potential (bit line potential) VBIT by a predetermined control voltage VX. A source/gate voltage Vsg of N type MOSFETS: QN1, QN2 is reduced by the Vs. According to a sensitivity of sub sense amplifiers, an output VOUT is enlarged to the judgment potential VBIT and a consumption current is reduced. The control voltage VX preferably satisfies (source/gate voltage Vsg-threshold voltage Vt)

5. 发明专利

JPS6368932A INFORMATION PROCESSOR 失效
公开(公告)号：JPS6368932A
公开(公告)日：1988-03-28
申请号：JP21361086
申请日：1986-09-10
申请人： MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP , SHARP KK
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , TOKURA TAKESHI , TAKAKURA MINORU , HARA HIDEJI , NISHIKAWA YOICHIRO , AKECHI MITSUO , OKAMOTO TOSHIYA , KOMATSU KOJI
IPC分类号： G06F15/82 , G06F9/44
摘要： PURPOSE:To perform proper input limitation by providing an input control part and sending external input data corresponding to an input permission token generated according to the execution of an input instruction to an information processor main body. CONSTITUTION:A processing element 1 equipped with the information processor main body 8, a network 6 in a processing element, etc., is provided with an input control part 8 which receives the external input data through the network 6. This control part 6 controls the external input data to the main body 8 by receiving the input permission token generated when the main body 8 executes an instruction indicated in the driving program of a program storage part 3 by an arithmetic part 5 for operand data passed from a queuing part 4. Therefore, input limitation is performed properly even for a program which varies in processed variable with an input data value to prevent the processor main body from stopping owing to an excessive input and the throughput from decreasing owing to the input limitation.

6. 发明专利

JP2000173286A SEMICONDUCTOR STORAGE 失效
公开(公告)号：JP2000173286A
公开(公告)日：2000-06-23
申请号：JP34223698
申请日：1998-12-01
申请人： SHARP KK
发明人： KOMATSU KOJI
IPC分类号： G11C17/18 , G11C7/00 , G11C8/14 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To reduce a chip area by reducing bank selection lines and to prevent delay of access caused by that a same word line group is inputted to adjacent bank regions by sharing a bank selection line between adjacent bank regions. SOLUTION: In this semiconductor memory, plural bank regions BNK in which memory cells are arranged in a matrix state are arranged in the direction of column, and the adjacent bank regions BNK are activated simultaneously. In this case, a word line group WL outputted by a common row decoder is inputted to the plural bank regions BNK, and a different word line group WL is inputted to adjacent bank region BNK.

7. 发明专利

JP2000124338A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JP2000124338A
公开(公告)日：2000-04-28
申请号：JP29588798
申请日：1998-10-16
申请人： SHARP KK
发明人： SUMINAGA YASUO , KOMATSU KOJI
IPC分类号： H01L23/00 , G11C5/06 , G11C17/12 , H01L27/112
摘要： PROBLEM TO BE SOLVED: To lighten the load of main bit lines and enable a high speed access by making a plurality of sub-bit lines of a first bank independent of sub-bit lines of a second bank and selecting two sub-bits in a bank having memory cells when reading data. SOLUTION: Sub-bit lines SB... of a bank BNK1 are made independent of sub-bit lines SB... of a bank BNK0 or BNK2. When reading data, only first switches TB12, TB21 and second switches TC14, TC16 are selected. A main bit line MB2 (or MB1) is hence electrically connected to the sub-bit line SB14 (or SB15) through the second switch TC16 (or TC14), a second subconductive region BC21 (or BC12), the first switch TB21 (or TB12) and a contact CT21 (or CT11). Remaining sub-bit lines SB11-SB13, SB16-SB19 are electrically insulated from the main bit lines MB1, MB2.

8. 发明专利

JPH10321793A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10321793A
公开(公告)日：1998-12-04
申请号：JP13223897
申请日：1997-05-22
申请人： SHARP KK
发明人： IMURA KOJI , TACHIKAWA MASAAKI , KOMATSU KOJI
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
摘要： PROBLEM TO BE SOLVED: To enable constituting a double-sided board mounting type semiconductor integrated circuit device constituted of an integrated circuit chip, having a board bias generating circuit and an integrated circuit chip which does not have a board bias generating circuit, without incurring cost increase. SOLUTION: This device is a resin-molded type semiconductor integrated circuit device, wherein a DRAM chip 11 and a mask ROM chip 12 are mounted on the both surface of a chip-mounting part 15 of a conductive lead frame, and the parts between the respective electrodes of the respective ships and the respective lead terminals are connected by bonding wires. The device is so constituted that the DRAM chip 11 has a board bias generating circuit 13, and the other mask ROM chip 12 does not have a board bias generating circuit. The threshold voltage of a MOS transistor arranged in the mask ROM chip 12 which does not have the board bias generating circuit is set to be lower than that of the case that a semiconductor integrated circuit device is constituted by molding only the mask ROM chip 12 with resin.

9. 发明专利

JPH10268859A FONT GENERATOR AND FONT GENERATOR DEVICE 失效
公开(公告)号：JPH10268859A
公开(公告)日：1998-10-09
申请号：JP6782197
申请日：1997-03-21
申请人： SHARP KK
发明人： MIYAMOTO YUKIO , KOMATSU KOJI , YOSHIMOTO TAKAHIKO
IPC分类号： B41J5/44 , G09G5/24
摘要： PROBLEM TO BE SOLVED: To make a free area continuous when a character dot matrix pattern of such a size that is not adaptable to the second power is stored. SOLUTION: To store a dot matrix pattern of 12 dots by 12 dots which is not adaptable to the second power in a font generator with 256-kbit storage capacity, a combination (1, 1) of addresses A14 and A15 of the high-order two bits is assigned to a free area formed in a one-character area 14. Thus, the free area of the whole on-character area is made present continuously on the high-order address side in the address space of the font generator.

10. 发明专利

JPH10228794A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH10228794A
公开(公告)日：1998-08-25
申请号：JP2994597
申请日：1997-02-14
申请人： SHARP KK
发明人： OKADA MIKIRO , KOMATSU KOJI
IPC分类号： G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory in which the read-out speed in accordance with kinds of memory data can be obtained without causing needless power consumption in a word line driving circuit. SOLUTION: In a semiconductor memory storing data of a first kind requiring read-out speed being comparatively high (for example, program data), and data of a second kind being lower read-out speed than that of the data (for example, character font data), the device is provided with two kinds of memory cell arrays I1 , I2 in which its word line length is different from each other, the data of the first kind is stored in the memory cell array I1 in which its word line length is short, and the data of the second kind is stored in the memory cell array I2 in which its word line length is long.

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