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1. 发明授权

EP0849783B1 Method of forming directionally deposited silicide on transistor electrodes 失效
标题翻译：一种用于生产的定向沉积在硅化物晶体管的电极的过程
公开(公告)号：EP0849783B1
公开(公告)日：2006-08-09
申请号：EP97308115.1
申请日：1997-10-14
申请人： SHARP KABUSHIKI KAISHA , SHARP MICROELECTRONICS TECHNOLOGY, INC.
发明人： Maa, Jer-shen , Hsu, Sheng Teng
IPC分类号： H01L21/60 , H01L21/768
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L2924/0002 , Y10S148/147 , H01L2924/00

2. 发明公开

EP0849783A3 Directionally deposited silicide on transistor electrodes and method for same 失效
标题翻译：晶体管的电极和制造工艺涉及硅化幽
公开(公告)号：EP0849783A3
公开(公告)日：1999-01-13
申请号：EP97308115.1
申请日：1997-10-14
申请人： SHARP KABUSHIKI KAISHA , SHARP MICROELECTRONICS TECHNOLOGY, INC.
发明人： Maa, Jer-shen , Hsu, Sheng Teng
IPC分类号： H01L21/60 , H01L21/768
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L2924/0002 , Y10S148/147 , H01L2924/00
摘要： A method is provided for forming silicide surfaces on source, drain, and gate electrodes in active devices to decrease the resistance of the electrode surfaces, without consuming the silicon of the electrodes in the process. Silicide is directionally deposited on the electrodes so that a greater thickness accumulates on electrode surfaces, and a lesser thickness accumulates on the gate sidewall surfaces isolating the gate from the source/drain electrodes. Then, the electrodes are isotropically etched so that the lesser thickness on the sidewalls is removed, leaving at least some thickness of silicide covering the electrodes. In further steps, the electrodes are masked with photoresist, and any silicide deposited in the region of field oxide around the electrodes is removed. Conductive lines, connecting to the electrodes across the field oxide, are fabricated from polycide, which includes a level of polysilicon covered with silicide, when the lower resistance surface of a metal-disilicide overlying the conductive line is required. The method of the present invention is applicable to bulk silicon, as well as SIMOX, transistor fabrication processes. An IC structure having different thicknesses of directionally deposited silicide, and a completed MOS transistor having interim thicknesses of directionally deposited silicide, are also provided.

3. 发明公开

EP0999597A1 Ferroelectric nonvolatile transistor and method of making same 有权
标题翻译： Ferroelektrischernichtflüchtiger晶体管和dessen Herstellungsverfahren
公开(公告)号：EP0999597A1
公开(公告)日：2000-05-10
申请号：EP99307192.7
申请日：1999-09-10
申请人： SHARP KABUSHIKI KAISHA
发明人： Hsu, Sheng Teng , Zhang, Fengyang , Maa, Jer-shen , Li, Tingkai
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/6684 , H01L29/78391
摘要： A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of δ, includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2 ≥ L1 + 2δ ; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure.
A ferroelectric memory transistor includes a silicon substrate having a p- well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2 ≥ L1 + 2δ, wherein δ is the alignment tolerance of the lithographic process.
摘要翻译：使用具有对准公差δ的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p-阱; 隔离基板上的多个器件区域; 形成FE门堆叠环绕结构; 蚀刻FE栅堆叠环绕结构以形成具有L1宽度的开口以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2≥L1+2δ; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并对结构进行金属化。铁电存储晶体管包括其中具有p-阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅堆叠环绕结构，所述开口具有围绕所述栅极区域的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2≥L1+2δ，其中Δ是光刻工艺的对准公差。

4. 发明公开

EP0849783A2 Directionally deposited silicide on transistor electrodes and method for same 失效
标题翻译：维尔法赫尔·冯·格里希特·阿格伯森·西尔西德·überTransistorelektroden
公开(公告)号：EP0849783A2
公开(公告)日：1998-06-24
申请号：EP97308115.1
申请日：1997-10-14
申请人： SHARP KABUSHIKI KAISHA , SHARP MICROELECTRONICS TECHNOLOGY, INC.
发明人： Maa, Jer-shen , Hsu, Sheng Teng
IPC分类号： H01L21/60 , H01L21/768
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L2924/0002 , Y10S148/147 , H01L2924/00
摘要： A method is provided for forming silicide surfaces on source, drain, and gate electrodes in active devices to decrease the resistance of the electrode surfaces, without consuming the silicon of the electrodes in the process. Silicide is directionally deposited on the electrodes so that a greater thickness accumulates on electrode surfaces, and a lesser thickness accumulates on the gate sidewall surfaces isolating the gate from the source/drain electrodes. Then, the electrodes are isotropically etched so that the lesser thickness on the sidewalls is removed, leaving at least some thickness of silicide covering the electrodes. In further steps, the electrodes are masked with photoresist, and any silicide deposited in the region of field oxide around the electrodes is removed. Conductive lines, connecting to the electrodes across the field oxide, are fabricated from polycide, which includes a level of polysilicon covered with silicide, when the lower resistance surface of a metal-disilicide overlying the conductive line is required. The method of the present invention is applicable to bulk silicon, as well as SIMOX, transistor fabrication processes. An IC structure having different thicknesses of directionally deposited silicide, and a completed MOS transistor having interim thicknesses of directionally deposited silicide, are also provided.
摘要翻译：提供了一种用于在有源器件中的源极，漏极和栅电极上形成硅化物表面以降低电极表面的电阻而不消耗该工艺中的电极的硅的方法。硅化物被定向沉积在电极上，使得更大的厚度积聚在电极表面上，并且较小的厚度积聚在栅极侧壁表面上，隔离栅极与源极/漏极电极。然后，电极被各向同性地蚀刻，以便去除侧壁上较小的厚度，留下覆盖电极的至少一些厚度的硅化物。在另外的步骤中，电极被光致抗蚀剂掩蔽，并且去除沉积在电极周围的场氧化物区域中的任何硅化物。连接到场氧化物两端的电极的导电线由聚硅氧烷制成，当需要覆盖在导电线上的金属二硅化物的较低电阻表面时，其包括一层覆盖有硅化物的多晶硅。本发明的方法可应用于体硅，以及SIMOX晶体管制造工艺。还提供了具有不同厚度的定向沉积的硅化物的IC结构和具有定向沉积的硅化物的中间厚度的完整的MOS晶体管。

5. 发明授权

EP0999597B1 Ferroelectric nonvolatile transistor and method of making same 有权
标题翻译：一种铁电非易失性晶体管及其制造方法
公开(公告)号：EP0999597B1
公开(公告)日：2006-01-18
申请号：EP99307192.7
申请日：1999-09-10
申请人： SHARP KABUSHIKI KAISHA
发明人： Hsu, Sheng Teng , Zhang, Fengyang , Maa, Jer-shen , Li, Tingkai
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/6684 , H01L29/78391

6. 发明公开

EP1054441A3 Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier and method for its fabrication 审中-公开
$Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier and method for its fabrication$
标题翻译：伴随的难熔金属和制造过程的复合隔挡铱 - 金属 - 氧垒结构
公开(公告)号：EP1054441A3
公开(公告)日：2003-01-02
申请号：EP00304334.6
申请日：2000-05-22
申请人： SHARP KABUSHIKI KAISHA
发明人： Zhang, Fengyan , Maa, Jer-shen , Hsu, Sheng Teng , Zhuang, Wei-Wei
IPC分类号： H01L21/02 , H01L21/285 , H01L21/768
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/55
摘要： An Ir-M-O composite film (16) has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer (14) made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir-M-O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir-M-O composite film barrier layer (16) and an Ir-M-O composite film ferroelectric electrode are also provided.
摘要翻译： IR-M-O复合膜-已经提供确实处于铁电电容器，其中，M包括各种难熔金属中的电极的形成是有用的。红外组合电影是在氧环境中的高温退火抗性。当与在从同一品种M转换金属制成下面的阻挡层使用，所得到的导电阻挡，从而禁止与Ir扩散到任何底层Si衬底。其结果是，IR硅化物的产品不形成，其降低了电极的界面特性。即，组合的Ir电影保持导通，不剥离或形成小丘，在高温退火过程中，即使在氧气。的IR-M-O导电电极/势垒结构是在非易失性FeRAM的设备，DRAM中，电容器，热电型红外线传感器，光学显示器，光学开关，压电换能器是有用的，并且表面声波装置。因此，提供一种用于在铱-M-O复合膜阻挡层和Ir-M-O复合薄膜铁电电极形成方法。

7. 发明公开

EP1054441A2 Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier and method for its fabrication 审中-公开
$Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier and method for its fabrication$
标题翻译：伴随的难熔金属和制造过程的复合隔挡铱 - 金属 - 氧垒结构
公开(公告)号：EP1054441A2
公开(公告)日：2000-11-22
申请号：EP00304334.6
申请日：2000-05-22
申请人： SHARP KABUSHIKI KAISHA
发明人： Zhang, Fengyan , Maa, Jer-shen , Hsu, Sheng Teng , Zhuang, Wei-Wei
IPC分类号： H01L21/02 , H01L21/285
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/55
摘要： An Ir-M-O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir-M-O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir-M-O composite film barrier layer and an Ir-M-O composite film ferroelectric electrode are also provided.

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