专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2013115900A1 REDUCING WEAK- ERASE TYPE READ DISTURB IN 3D NAND NON- VOLATILE MEMORY 审中-公开
标题翻译：减少3D NAND非易失性存储器中的弱读取干扰
公开(公告)号：WO2013115900A1
公开(公告)日：2013-08-08
申请号：PCT/US2012/066460
申请日：2012-11-23
申请人： SANDISK TECHNOLOGIES, INC. , DONG, Yingda , MUI, Man, L. , MIWA, Hitoshi
发明人： DONG, Yingda , MUI, Man, L. , MIWA, Hitoshi
IPC分类号： G11C11/56 , G11C16/04 , G11C16/26 , G11C16/34 , H01L27/115
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3427 , H01L27/1157 , H01L27/11582
摘要： A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non- conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.
摘要翻译：用于3D堆叠存储器件的读取过程为未选择的存储器串提供最佳级别的通道升压，以抑制正常和弱擦除类型的读取干扰。通过控制位线（Vbl），漏极侧选择栅极（Vsgd_unsel），源极选择栅极（Vsgs_unsel），存储器件的选定电平（字线层）（Vcg_sel）的电压，以及未选择的内存设备级别（Vcg_unsel）。通过初始使漏极侧和源极选择栅极不导通，可以提高通道，以允许来自增加的Vcg_unsel的电容耦合。然后通过升高Vsgd_unsel和/或Vsgs_unsel来使漏极侧和/或源极侧选择栅极导通，从而中断升压。另外，当Vcg_unsel仍在增加时，通过使漏极侧和/或源极侧选择栅极再次导通，可以发生升压。或者，通道可以在Vbl驱动。两级升压驱动Vbl上的通道，然后通过电容耦合提供升压。

IPRDB

热门服务

关于我们

友情链接

联系方式