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1. 发明申请

WO2013101554A1 METABLOCK SIZE REDUCTION USING ON CHIP PAGE SWAPPING BETWEEN PLANES 审中-公开
标题翻译：使用在平面图之间切换页面的代码大小减少
公开(公告)号：WO2013101554A1
公开(公告)日：2013-07-04
申请号：PCT/US2012/070360
申请日：2012-12-18
申请人： SANDISK TECHNOLOGIES INC.
发明人： SPROUSE, Steven , GOROBETS, Sergey, Anatolievich
IPC分类号： G11C7/10 , G11C11/56 , G11C16/10
CPC分类号： G11C7/1012 , G11C11/5621 , G11C16/10
摘要： Methods and systems are disclosed herein for storing data in a memory device. Data for multiple pages is written in parallel using plane interleaving. For example, in a four plane write, a first set of four pages are written in the following sequence: 0, 1, 2, 3. A second set of four pages, after plane interleaving, are written in the following sequent: 7, 4, 5, 6. After writing the data, the pages of written data are read, page swapped if necessary, and then written into another portion of memory (such as MLC).
摘要翻译：本文公开了用于将数据存储在存储器件中的方法和系统。使用平面交错并行写入多页数据。例如，在四平面写入中，按照以下顺序写入第一组四页：0,1,2,3。在平面交织之后的第二组四页被写入随后的后续步骤：7，写入数据后，读取写入数据的页面，如果需要，页面交换，然后写入存储器的另一部分（如MLC）。

2. 发明申请

WO2013101585A1 HYBRID MULTI-LEVEL CELL PROGRAMMING SEQUENCES 审中-公开
标题翻译：混合多级细胞编程序列
公开(公告)号：WO2013101585A1
公开(公告)日：2013-07-04
申请号：PCT/US2012/070557
申请日：2012-12-19
申请人： SANDISK TECHNOLOGIES INC.
发明人： SPROUSE, Steven , AVILA, Chris , GOROBETS, Sergey, Anatolievich
IPC分类号： G11C11/56 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/10
摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC, whether the specified data is part of a dataset that will fill a block, and other criteria.
摘要翻译：存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。每个编程技术在MLC中建立代表多个数据位的电荷配置。存储器件使用所选的编程技术将指定的数据写入MLC。在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。可以基于各种各样的标准来进行选择，包括数据是否已经先前写入到包括MLC的块，指定数据是否是将填充块的数据集的一部分以及其他标准。

3. 发明申请

WO2012158455A1 FAST TRANSLATION INDICATOR TO REDUCE SECONDARY ADDRESS TABLE CHECKS IN A MEMORY DEVICE 审中-公开
标题翻译：快速翻译指示符，以减少存储器件中的二次地址表检查
公开(公告)号：WO2012158455A1
公开(公告)日：2012-11-22
申请号：PCT/US2012/037287
申请日：2012-05-10
申请人： SANDISK TECHNOLOGIES INC. , GOROBETS, Sergey, Anatolievich , WU, William , SPROUSE, Steven, T.
发明人： GOROBETS, Sergey, Anatolievich , WU, William , SPROUSE, Steven, T.
IPC分类号： G06F3/06
CPC分类号： G06F3/064 , G06F3/0611 , G06F3/0679 , G06F12/0223 , G06F12/10 , G06F12/1009
摘要： A system and method for reducing the need to check both a secondary address table and a primary address table for logical to physical translation tasks is disclosed. The method may include generating a fast translation indicator, such as a logical group bitmap, indicating whether there is an entry in the secondary address table that contains desired information pertaining to a particular logical address. Upon a host request relating to the particular logical address, the storage device may check the bitmap to determine if retrieval and parsing of the secondary table is necessary. The system may include a storage device having RAM cache storage, flash storage and a controller configured to generate and maintain at least one fast translation indicator to reduce the need to check both secondary and primary address tables during logical to physical address translation operations of the storage device.
摘要翻译：公开了一种用于减少检查辅助地址表和用于逻辑到物理转换任务的主地址表的需要的系统和方法。该方法可以包括生成快速转换指示符，例如逻辑组位图，指示辅助地址表中是否存在包含与特定逻辑地址相关的期望信息的条目。在与特定逻辑地址相关的主机请求时，存储设备可以检查位图以确定是否需要检索和解析辅助表。该系统可以包括具有RAM高速缓存存储器，闪存存储器和被配置为生成和维护至少一个快速转换指示符的存储设备，以减少在存储器的逻辑到物理地址转换操作期间检查辅助和主地址表的需要设备。

4. 发明申请

WO2013101573A1 SLC-MLC WEAR BALANCING 审中-公开
标题翻译： SLC-MLC磨损平衡
公开(公告)号：WO2013101573A1
公开(公告)日：2013-07-04
申请号：PCT/US2012/070467
申请日：2012-12-19
申请人： SANDISK TECHNOLOGIES INC.
发明人： CHEN, Jian , GOROBETS, Sergey, Anatolievich , SPROUSE, Steven
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7211 , G11C16/349 , G11C2211/5641
摘要： A method and system for SLC-MLC Wear Balancing in a flash memory device is disclosed. The flash memory device includes a single level cell (SLC) portion (1002) and a multi-level cell (MLC) portion (1004). The age of the SLC portion and the MLC portion may differ, leading potentially to one portion wearing out before the other. In order to avoid this, a controller is configured to receive an age indicator from one or both of the SLC portion and the MLC portion, determine, based on the age indicator, whether to modify operation of the SLC portion and/or the MLC portion, and in response to determining to modifying operation, modify the operation of the at least one of the SLC portion or the MLC portion. The modification of the operation may thus balance wear between the SLC and MLC portions, thereby potentially extending the life of the flash memory device.
摘要翻译：公开了一种用于闪存设备中的SLC-MLC磨损平衡的方法和系统。闪速存储器件包括单电平单元（SLC）部分（1002）和多电平单元（MLC）部分（1004）。 SLC部分和MLC部分的时代可能不同，潜在地导致在另一部分之前磨损的部分。为了避免这种情况，控制器被配置为从SLC部分和MLC部分中的一个或两个接收年龄指示符，基于年龄指示符确定是否修改SLC部分和/或MLC部分的操作并且响应于确定修改操作，修改SLC部分或MLC部分中的至少一个的操作。因此，操作的修改可以平衡SLC和MLC部分之间的磨损，从而潜在地延长闪存设备的寿命。

5. 发明申请

WO2015102894A1 METHOD AND SYSTEM FOR ADJUSTING BLOCK ERASE OR PROGRAM PARAMETERS BASED ON A PREDICTED ERASE LIFE 审中-公开
标题翻译：基于预测的消除生命调整块删除或程序参数的方法和系统
公开(公告)号：WO2015102894A1
公开(公告)日：2015-07-09
申请号：PCT/US2014/070759
申请日：2014-12-17
申请人： SANDISK TECHNOLOGIES INC.
发明人： DARRAGH, Neil, Richard , EREZ, Eran , GOROBETS, Sergey, Anatolievich
IPC分类号： G11C16/34
CPC分类号： G06F3/0653 , G06F3/0616 , G06F3/0679 , G06F2212/7211 , G11C16/16 , G11C16/3495
摘要： A method and system are disclosed for improved block erase cycle life prediction and block management in a non-volatile memory. The method includes the storage device tracking information relating to a first erase cycle count at which the block erase time exceeded a predetermined threshold relative to a first erase cycle at which this occurred in other blocks. Blocks having a later relative erase cycle at which the erase time threshold is exceeded are assumed to have a greater erase cycle life than those that need to exceed the erase time threshold at an earlier erase cycle. This information is used to adjust wear leveling in the form of free block selection, garbage collection block selection and other block management processes. Alternatively or in combination, the predicted erase cycle life information is used to adjust program and/or erase parameters such as erase voltage and time.
摘要翻译：公开了用于在非易失性存储器中改进块擦除周期寿命预测和块管理的方法和系统。该方法包括与第一擦除周期计数有关的存储装置跟踪信息，在该第一擦除周期计数，块擦除时间超过预定阈值，相对于其它块中发生的第一擦除周期。具有擦除时间阈值超过的较后相对擦除周期的块假设具有比在较早擦除周期期间需要超过擦除时间阈值的擦除周期寿命更长的擦除周期寿命。该信息用于以自由块选择，垃圾收集块选择和其他块管理过程的形式来调整磨损均衡。或者或组合地，预测的擦除周期寿命信息用于调整诸如擦除电压和时间的程序和/或擦除参数。

6. 发明授权

EP1941368B1 CORRECTED DATA STORAGE AND HANDLING METHODS 失效转让
标题翻译：程序进行数据存储和处置KORREGIERTE
公开(公告)号：EP1941368B1
公开(公告)日：2013-08-28
申请号：EP06816218.9
申请日：2006-10-04
申请人： SanDisk Technologies Inc.
发明人： GOROBETS, Sergey, Anatolievich , ELHAMIAS, Reuven , GONZALEZ, Carlos, J. , CONLEY, Kevin, M.
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/106 , G06F11/1068 , G11C16/3418 , G11C16/3431 , G11C29/76

7. 发明授权

EP2513905B1 NON-VOLATILE MEMORY AND METHOD WITH ATOMIC PROGRAM SEQUENCE AND WRITE ABORT DETECTION 失效转让
标题翻译： NOT性存储器和法核程序顺序的写作漏失鉴定
公开(公告)号：EP2513905B1
公开(公告)日：2015-07-08
申请号：EP10796565.9
申请日：2010-12-16
申请人： SanDisk Technologies Inc.
发明人： GOROBETS, Sergey, Anatolievich , DUSIJA, Gautam, Ashok
IPC分类号： G11C11/56 , G11C16/10 , G06F12/02
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/06 , G11C16/10 , G11C16/22

8. 发明公开

EP2798637A1 METABLOCK SIZE REDUCTION USING ON CHIP PAGE SWAPPING BETWEEN PLANES 有权转让
标题翻译： METABLOCKVERKLEINERUNG使用片上侧水平之间
公开(公告)号：EP2798637A1
公开(公告)日：2014-11-05
申请号：EP12812475.7
申请日：2012-12-18
申请人： SanDisk Technologies Inc.
发明人： SPROUSE, Steven , GOROBETS, Sergey, Anatolievich
IPC分类号： G11C7/10 , G11C11/56 , G11C16/10
CPC分类号： G11C7/1012 , G11C11/5621 , G11C16/10
摘要： Methods and systems are disclosed herein for storing data in a memory device. Data for multiple pages is written in parallel using plane interleaving. For example, in a four plane write, a first set of four pages are written in the following sequence: 0, 1, 2, 3. A second set of four pages, after plane interleaving, are written in the following sequent: 7, 4, 5, 6. After writing the data, the pages of written data are read, page swapped if necessary, and then written into another portion of memory (such as MLC).

9. 发明授权

EP1828906B1 SCRATCH PAD BLOCK 有权转让
标题翻译：刮板垫块
公开(公告)号：EP1828906B1
公开(公告)日：2014-09-10
申请号：EP05852895.1
申请日：2005-12-01
申请人： SanDisk Technologies Inc.
发明人： BENNETT, Alan, David , GOROBETS, Sergey, Anatolievich
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7203

10. 发明公开

EP2513905A1 NON-VOLATILE MEMORY AND METHOD WITH ATOMIC PROGRAM SEQUENCE AND WRITE ABORT DETECTION 失效转让
标题翻译： NOT性存储器和法核程序顺序的写作漏失鉴定
公开(公告)号：EP2513905A1
公开(公告)日：2012-10-24
申请号：EP10796565.9
申请日：2010-12-16
申请人： SanDisk Technologies, Inc.
发明人： GOROBETS, Sergey, Anatolievich , DUSIJA, Gautam, Ashok
IPC分类号： G11C11/56 , G11C16/10 , G06F12/02
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/06 , G11C16/10 , G11C16/22
摘要： A program operation in a non-volatile memory is segmented at predefined junctures into smaller segments for execution over different times. The predefined junctures are such that they allow unambiguous identification when restarting the operation in a next segment so that the operation can continue without having to restart from the very beginning of the operation. This is accomplished by requiring the programming sequence of each segment to be atomic, that is, to only terminate at a predetermined type of programming step. In a next segment, the terminating programming step is identified by detecting a predetermined pattern of ECC errors across a group of programmed wordlines.

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