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1. 发明申请

WO2011081990A1 ERASE COMMAND CACHING TO IMPROVE ERASE PERFORMANCE ON FLASH MEMORY 审中-公开
标题翻译：删除命令缓存以提高闪速存储器的擦除性能
公开(公告)号：WO2011081990A1
公开(公告)日：2011-07-07
申请号：PCT/US2010/061092
申请日：2010-12-17
申请人： SANDISK CORPORATION , HUTCHISON, Neil, D. , BENNETT, Alan, D. , GOROBETS, Sergey, A. , SPROUSE, Steven, T.
发明人： HUTCHISON, Neil, D. , BENNETT, Alan, D. , GOROBETS, Sergey, A. , SPROUSE, Steven, T.
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1016 , G06F2212/7205 , G06F2212/7208
摘要： Systems and methods are disclosed to reduce the number of partial logical groups that are erased by writing erase patterns to memory in a non- volatile memory system. When a non-aligned erase command is received, the logical addresses of data associated with the erase command may be marked as erased. If the logical group corresponds to the size of a physical metablock, the controller may also issue a physical erase command for complete logical groups within the erase command. For those parts of the erase command that encompass only partial logical groups, the ranges of the logical block addresses marked for erasure are stored. As subsequent erase commands are received the address ranges of the erase commands are added to the previously stored address ranges. When a set of erase commands spans an entire logical group, the logical group is marked for physical erasure in its entirety.
摘要翻译：公开了系统和方法，以通过在非易失性存储器系统中将擦除模式写入存储器来减少擦除的部分逻辑组的数量。当接收到不对准的擦除命令时，可以将与擦除命令相关联的数据的逻辑地址标记为擦除。如果逻辑组对应于物理元区块的大小，则控制器还可以对擦除命令内的完整逻辑组发出物理擦除命令。对于仅包含部分逻辑组的擦除命令的那些部分，存储标记为擦除的逻辑块地址的范围。随着接下来的擦除命令被接收，擦除命令的地址范围被添加到先前存储的地址范围。当一组擦除命令跨越整个逻辑组时，逻辑组被整体标记为物理擦除。

2. 发明申请

WO2011075594A1 NON-VOLATILE MEMORY WITH MULTI-GEAR CONTROL USING ON-CHIP FOLDING OF DATA 审中-公开
标题翻译：使用片上数据折叠的多种控制的非易失性存储器
公开(公告)号：WO2011075594A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060844
申请日：2010-12-16
申请人： SANDISK CORPORATION , HUANG, Jianmin , AVILA, Chris , GAVENS, Lee M. , SPROUSE, Steven T. , GOROBETS, Sergey Anatolievich , HUTCHISON, Neil David
发明人： HUANG, Jianmin , AVILA, Chris , GAVENS, Lee M. , SPROUSE, Steven T. , GOROBETS, Sergey Anatolievich , HUTCHISON, Neil David
IPC分类号： G11C16/10 , G11C11/56
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

3. 发明申请

WO2010080091A1 METHOD FOR USING A CAPTCHA CHALLENGE TO PROTECT A REMOVABLE MOBILE FLASH MEMORY STORAGE DEVICE 审中-公开
标题翻译：使用人机界面挑战来保护可移动移动闪速存储器存储设备的方法
公开(公告)号：WO2010080091A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/006173
申请日：2009-11-17
申请人： SANDISK CORPORATION , SPROUSE, Steven, T. , GONZALEZ, Carlos, J. , BARZILAI, Ron , PARIKH, Dhaval
发明人： SPROUSE, Steven, T. , GONZALEZ, Carlos, J. , BARZILAI, Ron , PARIKH, Dhaval
IPC分类号： G06F21/00
CPC分类号： G06F21/79 , G06F21/36 , G06F2221/2133
摘要： The embodiments described herein generally use a challenge to protect a removable mobile flash memory storage device, where the challenge may be in the form of a "Completely Automated Public Turing Test to Tell Computers and Humans Apart" ("CAPTCHA"). In one embodiment, a method is provided in which a removable mobile flash memory storage device receives a command from a host device, generates a CAPTCHA challenge, provides the CAPTCHA challenge to the host device, receives a response to the CAPTCHA challenge from the host device, determines if the response satisfies the CAPTCHA challenge, and performs the command only if the response satisfies the CAPTCHA challenge. In another embodiment, a removable mobile flash memory storage device is provided for performing these acts.
摘要翻译：本文描述的实施例通常使用保护可移动的移动闪存存储设备的挑战，其中挑战可以是“完全自动公共图灵测试以告知计算机和人类之外”（“CAPTCHA”）的形式。在一个实施例中，提供了一种方法，其中可移动移动闪存存储设备从主机设备接收命令，生成CAPTCHA挑战，向主机设备提供CAPTCHA挑战，从主机设备接收对CAPTCHA挑战的响应，确定响应是否满足CAPTCHA挑战，并且仅当响应满足CAPTCHA挑战时才执行命令。在另一个实施例中，提供了用于执行这些动作的可拆卸移动闪存存储设备。

4. 发明申请

WO2012158455A1 FAST TRANSLATION INDICATOR TO REDUCE SECONDARY ADDRESS TABLE CHECKS IN A MEMORY DEVICE 审中-公开
标题翻译：快速翻译指示符，以减少存储器件中的二次地址表检查
公开(公告)号：WO2012158455A1
公开(公告)日：2012-11-22
申请号：PCT/US2012/037287
申请日：2012-05-10
申请人： SANDISK TECHNOLOGIES INC. , GOROBETS, Sergey, Anatolievich , WU, William , SPROUSE, Steven, T.
发明人： GOROBETS, Sergey, Anatolievich , WU, William , SPROUSE, Steven, T.
IPC分类号： G06F3/06
CPC分类号： G06F3/064 , G06F3/0611 , G06F3/0679 , G06F12/0223 , G06F12/10 , G06F12/1009
摘要： A system and method for reducing the need to check both a secondary address table and a primary address table for logical to physical translation tasks is disclosed. The method may include generating a fast translation indicator, such as a logical group bitmap, indicating whether there is an entry in the secondary address table that contains desired information pertaining to a particular logical address. Upon a host request relating to the particular logical address, the storage device may check the bitmap to determine if retrieval and parsing of the secondary table is necessary. The system may include a storage device having RAM cache storage, flash storage and a controller configured to generate and maintain at least one fast translation indicator to reduce the need to check both secondary and primary address tables during logical to physical address translation operations of the storage device.
摘要翻译：公开了一种用于减少检查辅助地址表和用于逻辑到物理转换任务的主地址表的需要的系统和方法。该方法可以包括生成快速转换指示符，例如逻辑组位图，指示辅助地址表中是否存在包含与特定逻辑地址相关的期望信息的条目。在与特定逻辑地址相关的主机请求时，存储设备可以检查位图以确定是否需要检索和解析辅助表。该系统可以包括具有RAM高速缓存存储器，闪存存储器和被配置为生成和维护至少一个快速转换指示符的存储设备，以减少在存储器的逻辑到物理地址转换操作期间检查辅助和主地址表的需要设备。

5. 发明申请

WO2009020845A1 ENHANCED WRITE ABORT MECHANISM FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：增强了非易失性存储器的写入机制
公开(公告)号：WO2009020845A1
公开(公告)日：2009-02-12
申请号：PCT/US2008/071865
申请日：2008-08-01
申请人： SANDISK CORPORATION , SPROUSE, Steven, T. , PARIKH, Dhaval , KAPOOR, Arjun
发明人： SPROUSE, Steven, T. , PARIKH, Dhaval , KAPOOR, Arjun
IPC分类号： G11C16/00 , G11C29/00 , G11B20/10
CPC分类号： G11C16/30 , G11C5/143 , G11C16/225 , G11C29/02 , G11C29/021 , G11C2029/0409
摘要： In a non- volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a "low-voltage" signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the "low-voltage" signal is deasserted and to suspend writing data while the "low-voltage" signal is asserted. In response to assertion of the "low-voltage" signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the "low- voltage" signal.
摘要翻译：在具有由控制器控制的控制器和非易失性存储器阵列的非易失性存储器（NVM）器件中，电压监控器电路监视为NVM器件供电的电压源的输出。电压监控器电路可以是NVM器件的一部分或耦合到其上。电压监控器电路被配置为响应于检测到NVM器件供电的电压输出下降到预定值以下来断言“低电压”信号。控制器被配置为在“低电压”信号被断言时将数据写入存储器阵列，并且在“低电压”信号被断言时暂停写入数据。响应于“低电压”信号的断言，控制器完成写入周期/编程操作，如果挂起，并且在断言“低电压”信号期间防止任何额外的写周期/编程操作。

6. 发明申请

WO2011075572A1 MAINTAINING UPDATES OF MULTI-LEVEL NON-VOLATILE MEMORY IN BINARY NON-VOLATILE MEMORY 审中-公开
标题翻译：维持二级非易失性存储器中多级非易失性存储器的更新
公开(公告)号：WO2011075572A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060751
申请日：2010-12-16
申请人： SANDISK CORPORATION , GOROBETS, Sergey Anatolievich , WU, William S. , TRAISTER, Shai , LYASHUK, Alexander , SPROUSE, Steven, T.
发明人： GOROBETS, Sergey Anatolievich , WU, William S. , TRAISTER, Shai , LYASHUK, Alexander , SPROUSE, Steven, T.
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C2211/5641 , G11C2211/5643
摘要： A method of operating a memory system is presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first portion, where data is stored in a binary format, and a second portion, where data is stored in a multi-state format. The controller manages the transfer of data to and from the memory system and the storage of data on the non-volatile memory circuit. The method includes receiving a first set of data and storing this first set of data in a first location in the second portion of the non-volatile memory circuit. The memory system subsequently receives updated data for a first subset of the first data set. The updated data is stored in a second location in the first portion of the non-volatile memory circuit, where the controller maintains a logical correspondence between the second location and the first subset of the first set of data.
摘要翻译：提出了一种操作存储系统的方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有以二进制格式存储数据的第一部分和第二部分，其中数据以多状态格式存储。控制器管理到存储器系统和从存储器系统传送数据以及将数据存储在非易失性存储器电路上。该方法包括接收第一组数据并将该第一组数据存储在非易失性存储器电路的第二部分中的第一位置。存储器系统随后接收第一数据集的第一子集的更新数据。更新的数据被存储在非易失性存储器电路的第一部分中的第二位置，其中控制器维持第一组数据的第二位置和第一子集之间的逻辑对应关系。

7. 发明申请

WO2008021741A1 CONNECTOR WITH ESD PROTECTION 审中-公开
标题翻译：具有ESD保护的连接器
公开(公告)号：WO2008021741A1
公开(公告)日：2008-02-21
申请号：PCT/US2007/075067
申请日：2007-08-02
申请人： SANDISK CORPORATION , COLLANTES, JR., Patricio , MILLER, Robert, C. , SPROUSE, Steven, T. , PARIKH, Dhaval
发明人： COLLANTES, JR., Patricio , MILLER, Robert, C. , SPROUSE, Steven, T. , PARIKH, Dhaval
IPC分类号： H01R13/658
CPC分类号： H01R13/6582 , H01R2201/06
摘要： A Universal Serial Bus flash memory unit (100) having an electrically conductive housing (101) includes a spring (310) that provides an electrically conductive, low- resistance pathway between the housing and the metal shell of the Universal Serial Bus connector so that electrostatic charge can directly discharge from the housing to the metal shell instead of discharging through electronic components within the housing.
摘要翻译：具有导电壳体（101）的通用串行总线闪存单元（100）包括弹簧（310），其在壳体和通用串行总线连接器的金属壳之间提供导电的低电阻通路，使得静电电荷可以从壳体直接排出到金属壳体，而不是通过壳体内的电子部件排出。

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