专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008048812A1 FABRICATING NON-VOLATILE MEMORY WITH DUAL VOLTAGE SELECT GATE STRUCTURE 审中-公开
标题翻译：用双电压门控结构制造非易失性存储器
公开(公告)号：WO2008048812A1
公开(公告)日：2008-04-24
申请号：PCT/US2007/080745
申请日：2007-10-08
申请人： SANDISK CORPORATION , MOKHLESI, Nima , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , HIGASHITANI, Masaaki
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , G11C16/04
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.
摘要翻译：用于非易失性存储系统的选择栅极结构包括独立驱动的选择栅极和耦合电极。耦合电极与NAND串中的字线相邻，并且具有施加的电压，其减小相邻未选择的非易失性存储元件的栅极引起的漏极降低（GIDL）编程干扰。特别地，当相邻字线用于编程时，可以将高电压施加到耦合电极。当使用非相邻字线进行编程时，施加降低的电压。电压也可以根据其他编程标准设定。选择栅极由第一导电区域提供，而耦合电极由形成在第一导电区域上并与之隔离的第二导电区域提供。

2. 发明申请

WO2008048813A1 NON-VOLATILE MEMORY WITH DUAL VOLTAGE SELECT GATE STRUCTURE 审中-公开
标题翻译：具有双电压选择门结构的非易失性存储器
公开(公告)号：WO2008048813A1
公开(公告)日：2008-04-24
申请号：PCT/US2007/080746
申请日：2007-10-08
申请人： SANDISK CORPORATION , MOKHLESI, Nima , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , HIGASHITANI, Masaaki
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , G11C16/04
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A select gate structure (1260) for a non-volatile storage system includes a select gate (1022) and a coupling electrode (1023) which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage (Vces) applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criteria. The select gate is provided by a first conductive region (1230) while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.
摘要翻译：用于非易失性存储系统的选择栅极结构（1260）包括独立驱动的选择栅极（1022）和耦合电极（1023）。耦合电极与NAND串中的字线相邻，并且具有施加的电压（Vces），其减小相邻未选择的非易失性存储元件的栅极引起的漏极降低（GIDL）编程干扰。特别地，当相邻字线用于编程时，可以将高电压施加到耦合电极。当使用非相邻字线进行编程时，施加降低的电压。也可以根据其他编程标准设定电压。选择栅极由第一导电区域（1230）提供，而耦合电极由形成在第一导电区域上并与之隔离的第二导电区域提供。

3. 发明申请

WO2008036484A2 NONVOLATILE MEMORY WITH REDUCED COUPLING BETWEEN FLOATING GATES 审中-公开
标题翻译：非易失性存储器，浮动门之间耦合减少
公开(公告)号：WO2008036484A2
公开(公告)日：2008-03-27
申请号：PCT/US2007/076163
申请日：2007-08-17
申请人： SANDISK CORPORATION , CHIEN, Henry , MATAMIS, George , PHAM, Tuan , HIGASHITANI, Masaaki , HORIUCHI, Hidetaka , LUTZE, Jeffrey, W. , MOKHLESI, Nima , FONG, Yupin, Kawing
发明人： CHIEN, Henry , MATAMIS, George , PHAM, Tuan , HIGASHITANI, Masaaki , HORIUCHI, Hidetaka , LUTZE, Jeffrey, W. , MOKHLESI, Nima , FONG, Yupin, Kawing
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
摘要翻译：非易失性存储器阵列包括沿垂直于浮动单元连接在一起以形成串的方向的平面的横截面中具有倒T形形状的浮置栅极。相邻的串被浅沟槽隔离结构隔离。具有倒T形浮置栅极的阵列可以以自对准方式形成。

4. 发明申请

WO2012082223A2 NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES CONNECTED TO SINGLE SELECTION DEVICE 审中-公开
标题翻译：具有连接到单个选择设备的共享位线的非易失存储系统
公开(公告)号：WO2012082223A2
公开(公告)日：2012-06-21
申请号：PCT/US2011/056146
申请日：2011-10-13
申请人： SANDISK TECHNOLOGIES, INC. , MOKHLESI, Nima , DUNGA, Mohan, V. , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , DUNGA, Mohan, V. , HIGASHITANI, Masaaki
CPC分类号： H01L21/28273 , G11C16/0483 , H01L27/11519 , H01L27/11521
摘要： A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line.
摘要翻译：公开了一种非易失性存储系统，其包括连接到共享位线的同一块中的NAND串（或存储器单元的其它组）对。为了操作该系统，使用两条选择线，使得可以在块级选择共享位线的NAND串（或存储器单元的其它分组）。两个选择线连接到共享位线的每个NAND串（或存储器单元的其它组）的选择门。

5. 发明申请

WO2011149823A1 PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHRONIZED COUPLING 审中-公开
标题翻译：编程具有同步耦合的非易失性存储
公开(公告)号：WO2011149823A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/037526
申请日：2011-05-23
申请人： SANDISK TECHNOLOGIES, INC. , MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected tol5 a group of connected non-volatile storage elements. The set of word lines includes a selected word line(WLn), unselected word lines (WLn+1/WLn- 1) that are adjacent to the selected word line and other unselected word lines (WLunse1). After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage (Vpgm) and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels (Vint1, Vint2, Vint3 ) concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.
摘要翻译：用于编程非易失性存储器的过程能够通过相邻字线的同步耦合来实现更快的编程速度和/或更精确的编程。编程过程包括提高连接到一组连接的非易失性存储元件的一组字线的电压。该字线组包括与所选择的字线和其他未被选择的字线（WLunse1）相邻的所选字线（WLn），未选字线（WLn + 1 / WLn-1）。在对所述一组字线提升电压之后，所述处理包括将所选择的字线升高到编程电压（Vpgm），并将与所选字线相邻的未选字线提升到一个或多个电压电平（Vint1，Vint2， Vint3）同时将选定的字线提升到编程电压。程序电压使至少一个非易失性存储元件经历编程。

6. 发明申请

WO2010033409A1 DATA STATE-BASED TEMPERATURE COMPENSATION DURING SENSING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中感测期间基于数据状态的温度补偿
公开(公告)号：WO2010033409A1
公开(公告)日：2010-03-25
申请号：PCT/US2009/056405
申请日：2009-09-09
申请人： SANDISK CORPORATION , DUNGA, Mohan, V. , HIGASHITANI, Masaaki
发明人： DUNGA, Mohan, V. , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/26
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/26
摘要： Temperature effects in a non-volatile storage device are addressed by providing a data state-dependent, and optionally temperature dependent, sense current during verify and read operations. A different sense current (1) is provided for each data state (2), so that a common temperature coefficient (3) is realized for storage elements with different data states. The temperature coefficient for higher states can be reduced to that of lower states. During sensing, a sense time can be adjusted to achieve a desired sense current when a selected storage element is in a conductive state. A fixed voltage trip point may be maintained. During the sense time, a pre-charged capacitor discharges into a selected storage element such as via a bit line and NAND string, when the selected storage element is in a conductive state. The discharge level is translated to a current which is compared to a state-dependent, and optionally temperature dependent, reference current.
摘要翻译：通过在验证和读取操作期间提供数据状态相关的和可选的与温度相关的感测电流来解决非易失性存储设备中的温度效应。为每个数据状态（2）提供不同的感测电流（1），使得对于具有不同数据状态的存储元件实现共同的温度系数（3）。较高状态的温度系数可以降低到较低的状态。在感测期间，当所选择的存储元件处于导通状态时，可以调整感测时间以实现期望的感测电流。可以保持固定的电压跳变点。在感测时间期间，当所选存储元件处于导通状态时，预充电电容器通过位线和NAND串放电到选定的存储元件中。将放电电平转换为与状态相关的，并且可选地与温度相关的参考电流进行比较的电流。

7. 发明申请

WO2009123843A1 NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL 审中-公开
标题翻译：具有连接源和非易失性存储的非易失性存储
公开(公告)号：WO2009123843A1
公开(公告)日：2009-10-08
申请号：PCT/US2009/037049
申请日：2009-03-13
申请人： SANDISK CORPORATION , HIGASHITANI, Masaaki
发明人： HIGASHITANI, Masaaki
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/74
CPC分类号： H01L29/66825 , H01L21/743 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well.
摘要翻译：公开了一种非易失性存储装置，其包括形成在阱上的一组连接的非易失性存储元件，位于阱中的位线触点，位于阱中的源极线接触件，连接到该阱的位线位线接触，以及连接到源极线接触点和阱的源极线。

8. 发明申请

WO2007081642A2 FLASH DEVICES WITH SHARED WORD LINES 审中-公开
标题翻译：具有共享字线的闪存设备
公开(公告)号：WO2007081642A2
公开(公告)日：2007-07-19
申请号：PCT/US2006/062188
申请日：2006-12-15
申请人： SANDISK CORPORATION , HIGASHITANI, Masaaki
发明人： HIGASHITANI, Masaaki
CPC分类号： G11C16/0483 , G11C8/14 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates.
摘要翻译： NAND闪速存储器阵列的字线由同心的矩形形状的闭环形成，其具有大约是所使用的图案化工艺的最小特征尺寸的一半的宽度。所得到的电路具有连接在一起的字线，使得外围电路被共享。单独的擦除块由屏蔽板建立。

9. 发明申请

WO2006069184A1 EEPROM ARRAY WITH SELF-ALIGNED SHALLOW-TRENCH ISOLATION 审中-公开
标题翻译：具有自对准SHELLOW-TRENCH隔离的EEPROM阵列
公开(公告)号：WO2006069184A1
公开(公告)日：2006-06-29
申请号：PCT/US2005/046448
申请日：2005-12-19
申请人： SANDISK CORPORATION , PHAM, Tuan , HIGASHITANI, Masaaki
发明人： PHAM, Tuan , HIGASHITANI, Masaaki
IPC分类号： H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer (302), floating gate layer (306), inter-layer dielectric (308) and mask layer (310) across all regions of the substrate. After self-aligned shallow-trench isolation structures (STI) have been formed, these layers are removed from the peripheral regions and dielectrics (640, 860) of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer (970) is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.
摘要翻译：将存储器阵列和外围电路一起制成在单个衬底上的方法在衬底的所有区域上形成介电层（302），浮动栅层（306），层间电介质（308）和掩模层（310）。在形成自对准的浅沟槽隔离结构（STI）之后，这些层从周边区域移除，并且根据这些区域中的电路的电压在外围区域中形成不同厚度的电介质（640,860）。在存储器阵列和外围电路上形成导电层（970），以在存储器阵列中形成控制栅极，并在外围区域中形成栅电极。

10. 发明申请

WO2011011525A1 METHOD OF FORMING NANOSTRUCTURE-BASED NAND FLASH CELLS AND THE PERIPHERY CIRCUITS THEREOF 审中-公开
标题翻译：形成基于纳米结构的NAND闪存细胞及其周围电路的方法
公开(公告)号：WO2011011525A1
公开(公告)日：2011-01-27
申请号：PCT/US2010/042766
申请日：2010-07-21
申请人： SANDISK CORPORATION , PURAYATH, Vinod, Robert , KAI, James, K. , HIGASHITANI, Masaaki , ORIMOTO, Takashi , MATAMIS, George , CHIEN, Henry
发明人： PURAYATH, Vinod, Robert , KAI, James, K. , HIGASHITANI, Masaaki , ORIMOTO, Takashi , MATAMIS, George , CHIEN, Henry
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L27/11573 , H01L29/788 , Y10S438/962 , Y10S977/774 , Y10S977/936
摘要： Nanostructure-based charge storage regions (CSR1-CSR5) are included in non-volatile memory devices and integrated with the fabrication of select gates (SGl) and peripheral circuitry (PGl, PG2) One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
摘要翻译：基于纳米结构的电荷存储区域（CSR1-CSR5）被包括在非易失性存储器件中，并与选择栅极（SG1）和外围电路（PG1，PG2）的制造集成在一个衬底上施加一个或多个纳米结构涂层存储器阵列区域和外围电路区域。提供了用于从衬底的不需要的区域（例如选择栅极和外围晶体管的目标区域）去除纳米结构涂层的各种工艺。在一个实例中，使用基于自组装的工艺来形成一个或多个纳米结构涂层以在衬底的有源区上选择性地形成纳米结构。自组装允许形成彼此电隔离的纳米结构的离散线，而不需要对纳米结构涂层进行图案化或蚀刻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式