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1. 发明申请

WO2011031660A3 IDENTIFYING AT-RISK DATA IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中识别AT-RISK数据
公开(公告)号：WO2011031660A3
公开(公告)日：2011-05-12
申请号：PCT/US2010047951
申请日：2010-09-07
申请人： SANDISK CORP , PEI GEN , GU LANLAN , MOKHLESI NIMA , ALROD IDAN , SHARON ERAN , AFRIAT ITSHAK
发明人： PEI GEN , GU LANLAN , MOKHLESI NIMA , ALROD IDAN , SHARON ERAN , AFRIAT ITSHAK
IPC分类号： G11C16/34 , G06F11/10
CPC分类号： G11C16/3418 , G06F11/1072
摘要： The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.
摘要翻译：非易失性存储系统根据性能数据预测哪些块（或其他存储单元）会变得不好。预测这些块中的用户数据变差，可以将其重新编程为其他块，并且预测变坏的块可以从进一步的使用中移除。

2. 发明申请

WO2011031660A4 IDENTIFYING AT-RISK DATA IN NON-VOLATILE STORAGE 审中-公开
公开(公告)号：WO2011031660A4
公开(公告)日：2011-07-07
申请号：PCT/US2010047951
申请日：2010-09-07
申请人： SANDISK CORP , PEI GEN , GU LANLAN , MOKHLESI NIMA , ALROD IDAN , SHARON ERAN , AFRIAT ITSHAK
发明人： PEI GEN , GU LANLAN , MOKHLESI NIMA , ALROD IDAN , SHARON ERAN , AFRIAT ITSHAK
IPC分类号： G11C16/34 , G06F11/10
CPC分类号： G11C16/3418 , G06F11/1072
摘要： The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.

3. 发明申请

WO2008063970A3 OPERATION NAND NON-VOLATILE MEMORY WITH BOOST ELECTRODES 审中-公开
标题翻译：使用升压电极操作NAND非易失性存储器
公开(公告)号：WO2008063970A3
公开(公告)日：2008-07-31
申请号：PCT/US2007084461
申请日：2007-11-12
申请人： SANDISK CORP , MOKHLESI NIMA
发明人： MOKHLESI NIMA
IPC分类号： G11C16/04 , G11C11/56 , G11C16/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method for operating non- volatile memory having boost electrodes. The boosted electrodes are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost electrodes can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost electrodes assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost electrode can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost electrode contacts the substrate at a source/drain region, and a boost voltage is provided to the boost electrode via a source-side of the NAND string.
摘要翻译：一种用于操作具有升压电极的非易失性存储器的方法。升压电极被提供用于单独的NAND串，并且可以单独控制以辅助编程，验证和读取过程。升压电极可以通常被升压和单独放电，部分地基于目标编程状态或验证电平。升压电极有助于编程，从而可以减少字线上的编程和通过电压，从而减少诸如编程干扰的副作用。在验证期间，可以同时验证字线上的所有存储元素。升压电极在读取期间也可以辅助。在一种方法中，NAND串具有双源极选择栅极，在该源极/漏极区域之间，升压电极与衬底接触，并且经由NAND串的源极侧将升压电压提供给升压电极。

4. 发明申请

WO2005073977A2 VARIABLE CURRENT SINKING FOR COARSE/FINE PROGRAMMING OF NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器的粗略/精细编程的可变电流
公开(公告)号：WO2005073977A2
公开(公告)日：2005-08-11
申请号：PCT/US2005002208
申请日：2005-01-25
申请人： SANDISK CORP , GUTERMAN DANIEL C , MOKHLESI NIMA , FONG YUPIN
发明人： GUTERMAN DANIEL C , MOKHLESI NIMA , FONG YUPIN
IPC分类号： A43B13/18 , G11C11/56 , G11C16/10 , G11C16/34 , G11C27/00 , G11C16/00
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3481 , G11C27/005
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.
摘要翻译：通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

5. 发明申请

WO2007149677A3 METHOD FOR NON-REAL TIME REPROGRAMMING OF NON-VOLATILE MEMORY TO ACHIEVE TIGHTER DISTRIBUTION OF THRESHOLD VOLTAGES 审中-公开
标题翻译：非易失性存储器的非实时时间重建方法，用于实现阈值电压的分配
公开(公告)号：WO2007149677A3
公开(公告)日：2008-05-22
申请号：PCT/US2007069711
申请日：2007-05-25
申请人： SANDISK CORP , MOKHLESI NIMA
发明人： MOKHLESI NIMA
IPC分类号： G11C11/56 , G11C16/10
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C29/00 , G11C2211/5621
摘要： A set of non-volatile storage elements undergoes initial programming, after which a reprogramming, with higher verify levels, is performed in non-real time, such as when a control enters a standby mode, when no other read or write tasks are pending. The reprogramming can program pages in the set one at a time, stopping at a page boundary when another read or write task is pending, and restarting when the control become available again. Status flags can be provided to identify whether a page and/or the set has completed the reprogramming. In another aspect, a higher pass voltage is applied to unselected word lines during the reprogramming. In another aspect, an error count is determined using a default set of read voltages, and an alternative set of read voltages is selected if the count exceeds a threshold.
摘要翻译：一组非易失性存储元件经历初始编程，此后，具有较高验证级别的重新编程以非实时的方式执行，例如当控制进入待机模式时，当没有其他读取或写入任务未决时。重新编程可以一次编程一组中的页面，当另一个读取或写入任务正在等待时停止在页面边界，并在控件再次可用时重新启动。可以提供状态标志来识别页面和/或集合是否已经完成重新编程。在另一方面，在重新编程期间，对未选择的字线施加更高的通过电压。在另一方面，使用默认读取电压集来确定错误计数，并且如果计数超过阈值，则选择一组替代的读取电压。

6. 发明申请

WO2007076451A2 ALTERNATE SENSING TECHNIQUES FOR NON-VOLATILE MEMORIES 审中-公开
标题翻译：非挥发性记忆的替代感测技术
公开(公告)号：WO2007076451A2
公开(公告)日：2007-07-05
申请号：PCT/US2006062513
申请日：2006-12-21
申请人： SANDISK CORP , MOKHLESI NIMA , LUTZE JEFFREY W
发明人： MOKHLESI NIMA , LUTZE JEFFREY W
CPC分类号： G11C11/5642 , G11C7/1048 , G11C16/0483 , G11C2211/565
摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.
摘要翻译：本发明提供了一种用于感测存储器单元的方案。所选择的存储单元通过其通道放电到地，然后将电压电平放置在传统源上，并将另一个电压电平放置在控制栅上，并允许单元位线充电。存储单元的位线然后将充电直到位线电压变得足够高以截止任何进一步的单元导通。位线电压的升高将以一定的速率发生，并且取决于单元的数据状态，并且当位线达到足够高的电平时，单元将关闭，使得体效应影响存储单元阈值到达目前，当前基本上关闭。特定实施例执行多个这样的感测子操作，每个具有不同的控制栅极电压，但是在每个操作中通过对先前放电的单元通过其源极充电来感测多个状态。

7. 发明申请

WO2010117807A3 TWO PASS ERASE FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：用于非易失存储的两次擦除
公开(公告)号：WO2010117807A3
公开(公告)日：2010-12-16
申请号：PCT/US2010029246
申请日：2010-03-30
申请人： SANDISK CORP , LEE DANA , MOKHLESI NIMA , KHANDEL WAL ANUBHAV
发明人： LEE DANA , MOKHLESI NIMA , KHANDEL WAL ANUBHAV
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C11/5635
摘要： Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells' threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.
摘要翻译：本文公开了用于擦除非易失性存储器单元的技术。使用试验擦除脉冲擦除存储单元。基于试用擦除脉冲的幅度和在试验擦除之后关于阈值电压分布收集的数据来确定适合于第二脉冲的幅度。第二个擦除脉冲用于擦除存储单元。在一个实现中，在第二擦除之后，不会验证存储器单元的阈值电压。可以执行第二次擦除之后的软编程。可以基于试用擦除脉冲来确定软编程脉冲的幅度。在一个实现中，在软编程之后，不会验证存储单元的阈值电压。限制擦除脉冲数和软编程脉冲可节省时间和功率。确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

8. 发明申请

WO2008036552A3 ARRAY OF NON-VOLATILE MEMORY CELLS WITH FLOATING GATES FORMED OF SPACERS IN SUBSTRATE TRENCHES 审中-公开
标题翻译：具有在底板中形成间隔物的浮动栅的非易失性记忆细胞阵列
公开(公告)号：WO2008036552A3
公开(公告)日：2008-09-12
申请号：PCT/US2007078420
申请日：2007-09-13
申请人： SANDISK CORP , MOKHLESI NIMA
发明人： MOKHLESI NIMA
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11556 , H01L29/42336 , H01L29/7881
摘要： In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements (103, 105, 111, 113) are positioned along sidewalls of substrate trenches (60, 61), preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes cells with this structure, as an example. A NAND array of memory cells is another example of an application of this cell structure. The memory cell and array structures have wide application to various specific NOR and NAND memory cell array architectures.
摘要翻译：为了减少由给定数量的闪存单元的阵列占据的集成电路区域，浮置栅极电荷存储元件（103,105,111,113）沿着衬底沟槽（60,61）的侧壁定位，优选地由掺杂的多晶硅间隔物形成。作为示例，双浮栅存储器单元的阵列包括具有该结构的单元。存储器单元的NAND阵列是该单元结构的应用的另一示例。存储单元和阵列结构广泛地应用于各种特定的NOR和NAND存储器单元阵列架构。

9. 发明申请

WO2007143399A2 DATA PATTERN SENSITIVITY COMPENSATION USING DIFFERENT VOLTAGE 审中-公开
标题翻译：使用不同电压的数据模式灵敏度补偿
公开(公告)号：WO2007143399A2
公开(公告)日：2007-12-13
申请号：PCT/US2007069590
申请日：2007-05-23
申请人： SANDISK CORP , MOKHLESI NIMA , DONG YINGDA
发明人： MOKHLESI NIMA , DONG YINGDA
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Errors can occur when reading the threshold voltage of a programmed non- volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating gates, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. To account for the back pattern effect, a first voltage is used during a verify operation for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. The combination of these two techniques provides for more accurate storage and retrieval of data.
摘要翻译：读取编程非易失性存储元件的阈值电压时可能会发生错误，因为至少有两种机制：（1）相邻浮动栅极之间的电容耦合和（2）编程后改变通道区域的电导率（称为反向图案影响）。为了考虑相邻浮动栅极之间的耦合，对于特定存储器单元的读取处理将为相邻存储器单元提供补偿，以便减少相邻存储器单元对特定存储器单元具有的耦合效应。为了解决背模式效应，在对已经经过编程操作的未选字线的验证操作期间使用第一电压，并且对未经过编程操作的未选字线使用第二电压。这两种技术的组合提供了更准确的数据存储和检索。

10. 发明申请

WO2009035834A3 NONVOLATILE MEMORY AND METHOD FOR ON-CHIP PSEUDO-RANDOMIZATION OF DATA WITHIN A PAGE AND BETWEEN PAGES 审中-公开
标题翻译：非页面存储器和方法，用于在页面和页面之间的数据的片上PSEUDO-RANDOMIZATION
公开(公告)号：WO2009035834A3
公开(公告)日：2009-05-22
申请号：PCT/US2008073750
申请日：2008-08-20
申请人： SANDISK CORP , LI YAN , FONG YUPIN KAWING , MOKHLESI NIMA
发明人： LI YAN , FONG YUPIN KAWING , MOKHLESI NIMA
IPC分类号： G11C7/10 , G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C7/1006 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/5647
摘要： Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.
摘要翻译：集成电路存储芯片内的特征使得能够对存储在非易失性存储单元阵列中的数据进行加扰或随机化。在一个实施例中，每个页面内的随机化有助于控制感测期间的源负载误差和在相邻小区之间的浮动栅极到浮动栅极耦合。从页面到页面的随机化有助于减少程序干扰，用户读取干扰以及由特定数据模式的重复和长期存储引起的浮动栅极耦合的浮动栅极。在另一个实施例中，在页面之间和页面之间实现随机化。在不同的实施例中，加扰或随机化可以是预定的，或代码生成的伪随机化或用户驱动的随机化。这些功能在集成电路存储芯片的有限资源和预算内完成。

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