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1. 发明申请

WO2011127195A1 SAW-SHAPED MULTI-PULSE PROGRAMMING FOR PROGRAM NOISE REDUCTION IN MEMORY 审中-公开
标题翻译：存储器中程序噪声减少的SAW形状多脉冲编程
公开(公告)号：WO2011127195A1
公开(公告)日：2011-10-13
申请号：PCT/US2011/031452
申请日：2011-04-06
申请人： SANDISK CORPORATION , DONG, Yingda , FONG, Yupin, K. , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , FONG, Yupin, K. , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/10
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C2211/5621 , G11C2211/5622
摘要： In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.
摘要翻译：在存储器系统中，编程波形通过使用具有锯齿形状的多个相邻子脉冲的集合来减少编程噪声。在一组中，初始子脉冲从初始电平（例如0V）升高到峰值电平，然后降至高于初始电平的中间电平。集合的一个或多个后续子脉冲可以从中间电平升高到峰值电平，然后降低到中间电平。集合的最后一个子脉冲可以从中间电平升高到峰值电平，然后降低到初始电平。在子脉冲组之后执行验证操作。每组的子脉冲数可以在连续的集合中减小，直到在编程操作结束时施加孤立脉冲。

2. 发明申请

WO2008011439A3 COMPENSATING FOR COUPLING BETWEEN ADJACENT STORAGE ELEMENTS IN A NONVOLATILE MEMORY, BASED ON SENSING A NEIGHBOUR USING COUPLING 审中-公开
标题翻译：在非易失性存储器中的相似存储元件之间的耦合的补偿，基于使用耦合的感测邻域
公开(公告)号：WO2008011439A3
公开(公告)日：2008-07-24
申请号：PCT/US2007073737
申请日：2007-07-18
申请人： SANDISK CORP , FONG YUPIN , LI YAN
发明人： FONG YUPIN , LI YAN
IPC分类号： G11C11/56
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/3418
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。为了补偿该耦合，给定存储器单元的读取或编程过程可以考虑相邻存储器单元的编程状态。为了确定是否需要补偿，可以执行包括感测关于相邻存储器单元的编程状态的信息（例如，在相邻位线或其他位置上）的处理。

3. 发明申请

WO2007067447A1 REDUCING READ DISTURB FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：减少读取干扰非易失性存储
公开(公告)号：WO2007067447A1
公开(公告)日：2007-06-14
申请号：PCT/US2006/046126
申请日：2006-11-30
申请人： SANDISK CORPORATION , FONG, Yupin , WAN, Jun , LUTZE, Jeffrey
发明人： FONG, Yupin , WAN, Jun , LUTZE, Jeffrey
IPC分类号： G11C16/04 , G11C16/34
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C2211/5642
摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.
摘要翻译：公开了一种用于减少或去除非易失性存储装置中的读取干扰形式的系统。一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

4. 发明申请

WO2011156695A8 AIR GAP ISOLATION BETWEEN THE BIT LINES OF A NON-VOLATILE MEMORY AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：WO2011156695A8
公开(公告)日：2011-12-15
申请号：PCT/US2011/039955
申请日：2011-06-10
申请人： SANDISK TECHNOLOGIES, INC. , HARARI, Eli , PHAM, Tuan , FONG, Yupin , PURAYATH, Vinod, Robert
发明人： HARARI, Eli , PHAM, Tuan , FONG, Yupin , PURAYATH, Vinod, Robert
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/764
摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation can be provided, at least in part, by bit line air gaps that are elongated in a column direction and/or word line air gaps that are elongated in a row direction. The bit line air gaps (306) may be formed in the substrate, extending between adjacent active areas of the substrate, as well as above the substrate surface, extending between adjacent columns of non-volatile storage elements. The word line air gaps may be formed above the substrate surface, extending between adjacent rows of non-volatile storage elements.

5. 发明申请

WO2010042587A1 NONVOLATILE MEMORY AND METHOD WITH REDUCED PROGRAM VERIFY BY IGNORING FASTEST AND/OR SLOWEST PROGRAMMING BITS 审中-公开
标题翻译：非易失性存储器和方法通过点燃最慢和/或更慢的编程位置来减少程序验证
公开(公告)号：WO2010042587A1
公开(公告)日：2010-04-15
申请号：PCT/US2009/059799
申请日：2009-10-07
申请人： SANDISK CORPORATION , LI, Yan , FONG, Yupin, Kawing , CHAN, Siu Lung
发明人： LI, Yan , FONG, Yupin, Kawing , CHAN, Siu Lung
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

6. 发明申请

WO2010030701A1 BUILT IN ON-CHIP DATA SCRAMBLER FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：内置非易失性存储器的片上数据烧录器
公开(公告)号：WO2010030701A1
公开(公告)日：2010-03-18
申请号：PCT/US2009/056403
申请日：2009-09-09
申请人： SANDISK CORPORATION , WUN, Jun , FONG, Yupin, K. , MUI, Man, L.
发明人： WUN, Jun , FONG, Yupin, K. , MUI, Man, L.
IPC分类号： G11C7/10 , G11C16/10 , G11C16/34 , G11C16/04 , G11C16/00
CPC分类号： G11C7/1045 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26
摘要： A non-volatile memory in which data is randomized before being stored in the non-volatile memory to minimize data pattern-related read failures. Randomizing is performed using circuitry on the memory die so that the memory die is portable relative to an external, off-chip controller. Circuitry on the memory die scrambles user data based on a key which is generated using a seed which is shifted according to a write address. Corresponding on-chip descrambling is also provided.
摘要翻译：一种非易失性存储器，其中数据在被存储在非易失性存储器中之前被随机化以最小化与数据模式相关的读取故障。使用存储器管芯上的电路执行随机化，使得存储器管芯相对于外部的片外控制器是便携式的。存储器上的电路根据使用根据写入地址移位的种子生成的密钥对用户数据进行加扰。还提供了相应的片上解扰。

7. 发明申请

WO2008031074A1 PSEUDO RANDOM AND COMMAND DRIVEN BIT COMPENSATION FOR THE CYCLING EFFECTS IN FLASH MEMORY AND METHODS THEREFOR 审中-公开
标题翻译： FLASH存储器循环效应的PSEUDO随机和命令驱动位补偿及其方法
公开(公告)号：WO2008031074A1
公开(公告)日：2008-03-13
申请号：PCT/US2007/077940
申请日：2007-09-07
申请人： SANDISK CORPORATION , LI, Yan , FONG, Yupin Kawing
发明人： LI, Yan , FONG, Yupin Kawing
IPC分类号： G11C16/34 , G11C16/10 , G11C16/20 , G11C7/10 , G11C7/02 , G11C7/20
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/1039 , G11C7/1051 , G11C7/1063 , G11C7/20 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2207/2245
摘要： Easily implemented randomization within a flash memory EEPROM reduces the NAND string resistance effect, program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. The randomization may be code generated pseudo randomization or user driven randomization in different embodiments. User driven commands, the timing of which cannot be predicted may be used to trigger and achieve a high level of randomization. Randomly altering the encoding scheme of the data prevents repeated and long term storage of specific data patterns. Even if a user wishes to store the same information for long periods, or to repeatedly store it, it will be randomly encoded with different encoding schemes, and the data pattern will therefore be varied.
摘要翻译：易于实现的闪速存储器EEPROM内的随机化可以减少由于特定数据模式的重复和长期存储而导致的NAND串电阻效应，程序干扰，用户读取干扰以及浮动栅极到浮动栅极耦合。在不同的实施例中，随机化可以是代码生成的伪随机化或用户驱动的随机化。用户驱动的命令，其定时不能预测可用于触发并实现高水平的随机化。随机改变数据的编码方案可防止特定数据模式的重复和长期存储。即使用户希望长时间存储相同的信息，也可以重复存储，将以不同的编码方式进行随机编码，因此数据模式将会变化。

8. 发明申请

WO2009148906A1 ERASE-VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：非易失性存储的擦除验证过程
公开(公告)号：WO2009148906A1
公开(公告)日：2009-12-10
申请号：PCT/US2009/045358
申请日：2009-05-28
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , LEE, Shih-Chung , MIWA, Toru , FONG, Yupin , WAN, Jun , OOWADA, Ken
发明人： HEMINK, Gerrit, Jan , LEE, Shih-Chung , MIWA, Toru , FONG, Yupin , WAN, Jun , OOWADA, Ken
IPC分类号： G11C16/34
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non- volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non- volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功地擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

9. 发明申请

WO2008157606A1 INTELLIGENT CONTROL OF PROGRAM PULSE DURATION 审中-公开
标题翻译：智能控制程序脉冲持续时间
公开(公告)号：WO2008157606A1
公开(公告)日：2008-12-24
申请号：PCT/US2008/067347
申请日：2008-06-18
申请人： SANDISK CORPORATION , FONG, Yupin , WAN, Jun
发明人： FONG, Yupin , WAN, Jun
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.
摘要翻译：为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。编程脉冲具有恒定的脉冲宽度和增加的幅度，直到达到最大电压。在这一点上，编程脉冲的幅度停止增加，编程脉冲以一种方式施加，以便在验证操作之间提供编程信号的变化的持续时间。在一个实施例中，例如，在脉冲达到最大幅度之后，脉冲宽度增加。在另一个实施例中，在脉冲达到最大幅度之后，在验证操作之间施加多个编程脉冲。

10. 发明申请

WO2008011439A2 COMPENSATING FOR COUPLING BASED ON SENSING A NEIGHBOR USING COUPLING 审中-公开
标题翻译：基于使用耦合感测邻域的耦合补偿
公开(公告)号：WO2008011439A2
公开(公告)日：2008-01-24
申请号：PCT/US2007/073737
申请日：2007-07-18
申请人： SANDISK CORPORATION , FONG, Yupin , LI, Yan
发明人： FONG, Yupin , LI, Yan
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/3418
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。为了补偿该耦合，给定存储器单元的读取或编程过程可以考虑相邻存储器单元的编程状态。为了确定是否需要补偿，可以执行包括感测关于相邻存储器单元的编程状态的信息（例如，在相邻位线或其他位置上）的处理。

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