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1. 发明专利

AT527661T 未知
公开(公告)号：AT527661T
公开(公告)日：2011-10-15
申请号：AT05711926
申请日：2005-01-25
申请人： SANDISK CORP
发明人： GUTERMAN DANIEL , MOKHLESI NIMA , FONG YUPIN
IPC分类号： G11C16/00 , A43B13/18 , G11C11/56 , G11C16/10 , G11C16/34 , G11C27/00
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

2. 发明专利

AT496373T 未知
公开(公告)号：AT496373T
公开(公告)日：2011-02-15
申请号：AT04795181
申请日：2004-10-12
申请人： SANDISK CORP , TOSHIBA KK
发明人： CHEN JIAN , LUTZE JEFFREY , LI YAN , GUTERMAN DANIEL , TOMOHARU TANAKA
IPC分类号： G11C11/56 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).

3. 发明专利

AT448550T 未知
公开(公告)号：AT448550T
公开(公告)日：2009-11-15
申请号：AT05711892
申请日：2005-01-25
申请人： SANDISK CORP
发明人： GUTERMAN DANIEL , MOKHLESI NIMA , FONG YUPIN
IPC分类号： G11C16/10 , G11C11/56 , G11C27/00
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

4. 发明专利

AT511187T 未知
公开(公告)号：AT511187T
公开(公告)日：2011-06-15
申请号：AT05736981
申请日：2005-04-20
申请人： SANDISK CORP
发明人： GUTERMAN DANIEL , MOKHLESI NIMA , FONG YUPIN
IPC分类号： G11C16/10 , G11C11/56 , G11C16/04

5. 发明专利

DE60132830T2 未知
公开(公告)号：DE60132830T2
公开(公告)日：2009-02-05
申请号：DE60132830
申请日：2001-12-28
申请人： SANDISK CORP
发明人： CONLEY KEVIN M , GUTERMAN DANIEL , GONZALEZ CARLOS
IPC分类号： G11C16/02 , G11C16/34 , G11C11/15 , G11C13/00 , G11C16/06
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.

6. 发明专利

AU2001297851A8 Novel method and structure for efficient data verification operation for non-volatile memories 未知
公开(公告)号：AU2001297851A8
公开(公告)日：2005-11-03
申请号：AU2001297851
申请日：2001-12-28
申请人： SANDISK CORP
发明人： GUTERMAN DANIEL , CONLEY KEVIN M , GONZALEZ CARLOS
IPC分类号： G11C16/02 , G11C11/15 , G11C13/00 , G11C16/06 , G11C16/34
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.

7. 发明专利

AT257271T 未知
公开(公告)号：AT257271T
公开(公告)日：2004-01-15
申请号：AT99971140
申请日：1999-10-20
申请人： SANDISK CORP
发明人： CERNEA RAUL-ADRIAN , TANG RUSHYAH , LEE DOUGLAS , WANG CHI-MING , GUTERMAN DANIEL
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , G11C16/28
摘要： Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier. The improved sensing accuracy allows higher resolution of conduction states, thereby allowing a cell to store substantially more than one bit of information.

8. 发明专利

AU2001297851A1 Novel method and structure for efficient data verification operation for non-volatile memories 未知
公开(公告)号：AU2001297851A1
公开(公告)日：2002-12-16
申请号：AU2001297851
申请日：2001-12-28
申请人： SANDISK CORP
发明人： GUTERMAN DANIEL , CONLEY KEVIN M , GONZALEZ CARLOS
IPC分类号： G11C16/02 , G11C11/15 , G11C13/00 , G11C16/06 , G11C16/34
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.

9. 发明专利

AT535912T 未知
公开(公告)号：AT535912T
公开(公告)日：2011-12-15
申请号：AT04754703
申请日：2004-06-07
申请人： SANDISK CORP
发明人： GUTERMAN DANIEL , GROSS STEPHEN , KHALID SHAHZAD , GONGWER GEOFFREY
IPC分类号： G11C11/56 , G06F12/00 , G11C11/00 , G11C11/409 , G11C16/26 , G11C16/34
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Read operations are performed on the tracking cells, where threshold voltages of physical states of the tracking cells are further apart than threshold voltages of physical states of non-tracking cells. Based on the read operations, an extent to which the tracking cells are errored is determined.

10. 发明专利

AT516584T 未知
公开(公告)号：AT516584T
公开(公告)日：2011-07-15
申请号：AT05737998
申请日：2005-04-20
申请人： SANDISK CORP
发明人： GUTERMAN DANIEL , MOKHLESI NIMA , FONG YUPIN
IPC分类号： G11C16/10 , G11C11/56 , G11C16/04

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