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1. 发明授权

US06437781B1 Computer graphics system having per pixel fog blending 失效
公开(公告)号：US06437781B1
公开(公告)日：2002-08-20
申请号：US08866556
申请日：1997-05-30
申请人： S. Paul Tucker , Bradly J. Foster , Steven J. Kommrusch
发明人： S. Paul Tucker , Bradly J. Foster , Steven J. Kommrusch
IPC分类号： G06T1550
CPC分类号： G06T15/503
摘要： A computer graphics system includes an apparatus for fog blending colors to be displayed on a graphics display of the computer graphics system. The computer graphics system includes a rendering parameter calculation unit responsive to data of a primitive, that determines a cooked exponent value and a color value for at least one pixel of the primitive. In addition, the system includes a fog unit responsive to the cooked exponent value for each pixel of the primitive, that determines a fog blending factor for each pixel of the primitive, wherein the fog blending factor is one of an exponential fog blending factor and an exponential-squared fog blending factor. Further, the system includes a fog blending unit responsive to the color value and the fog blending factor for each pixel of the primitive and also to a fog color value, that blends the fog color value with the color value for each pixel of the primitive according to the fog blending factor for the respective pixel, and that provides a fogged color value for each pixel of the primitive. In addition, the computer graphics system may include a first interpolator, responsive to the color value and the cooked exponent value for at least one pixel of the primitive, that determines the color value and the cooked exponent value along an edge of the primitive so as to provide the cooked exponent value and the color value for each pixel of the edge of the primitive. Further, the computer graphics system may also include a second interpolator, responsive to the cooked exponent value and the color value for each pixel of the edge of the primitive, that determines the cooked exponent value and the color value along a span of the primitive so as to provide the cooked exponent value and the color value for each pixel of the span of the primitive. In this way, the system provides fast and accurate exponential and exponential-squared fog blending of the color values of the primitive without a lot of hardware.

2. 发明授权

US5446496A Frame rate conversion with asynchronous pixel clocks 失效
标题翻译：具有异步像素时钟的帧速率转换
公开(公告)号：US5446496A
公开(公告)日：1995-08-29
申请号：US221433
申请日：1994-03-31
申请人： Bradly J. Foster , David J. Hodge , Steven J. Kommrusch
发明人： Bradly J. Foster , David J. Hodge , Steven J. Kommrusch
IPC分类号： H04N5/04 , G09G3/20 , G09G5/00 , G09G5/39 , H04N7/01 , H04N9/64
CPC分类号： G09G5/005 , G09G5/39 , H04N7/01 , H04N7/0105 , G09G2340/0435 , G09G2360/18 , G09G5/006
摘要： A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control. Moreover, the display control synchronizes the writing and reading operations by the frame buffer control and the display control, respectively, each time that a frame has been skipped. Furthermore, the frame buffer control causes the VRAM frame buffer to transfer data from the split memory to the shift register when the horizontal blank is deasserted within the incoming analog video signal.
摘要翻译：帧速率转换系统将数据传输与来自并发，连续和异步的VRAM帧缓冲器进行同步。该系统包括具有用于将数据传送到分离输出移位寄存器的分离存储器的帧缓冲器。帧缓冲器控制以第一帧速率监视对分离存储器的写入操作。显示控制器以比第一帧速率慢的第二帧速率监视来自移位寄存器的读取操作。帧缓冲器控制和显示控制通过双同步器传送控制信号。显示控制具有用于计数从VRAM帧缓冲器读取的数据帧的计数器。显示控制防止在特定数量的帧被计数之后将帧写入分离存储器，以防止帧缓冲器控制通过显示器写入并破坏尚未从分离存储器读取的现有数据控制。此外，每当帧被跳过时，显示控制分别通过帧缓冲器控制和显示控制来同步写入和读取操作。此外，当输入模拟视频信号中的空白被取消置位时，帧缓冲器控制使得VRAM帧缓冲器将数据从分离存储器传送到移位寄存器。

3. 发明授权

US5539473A Dot clock generation with minimal clock skew 失效
标题翻译：点时钟生成，时钟偏移最小
公开(公告)号：US5539473A
公开(公告)日：1996-07-23
申请号：US543229
申请日：1995-10-13
申请人： Steven J. Kommrusch , Bradly J. Foster
发明人： Steven J. Kommrusch , Bradly J. Foster
IPC分类号： H04N5/06 , G09G5/18 , H04N5/12 , H04N5/04
CPC分类号： H04N5/126
摘要： A dot clock generation system has a voltage-controlled oscillator (VCO) for generating a dot clock signal for an analog-to-digital convertor (ADC). A dot clock synchronization (sync) generator counts cycles of the dot clock signal and generates a dot clock sync signal. An analog video signal is passed through a first differential buffer to create an analog video sync signal. The analog video sync signal is passed through a first flip-flop storage element to a phase detector. The dot clock sync signal is passed through a second storage element and then through a second differential buffer to the phase detector. The second storage buffer insures that the edge of the dot clock sync signal which is used by the phase detector is tightly tied with the sampling edge of the dot clock signal which is used by the ADC to sample the analog data within the analog video signal. Moreover, the first and second buffers and storage elements introduce similar propagation time delays into the analog video sync signal and the dot clock sync signal. Accordingly, the phase detector accurately compares the phases of these sync signals and generates a highly accurate voltage control signal for the voltage-controlled oscillator, thereby resulting in a high precision dot clock signal.
摘要翻译：点时钟发生系统具有用于产生用于模数转换器（ADC）的点时钟信号的压控振荡器（VCO）。点时钟同步（sync）发生器计数点时钟信号的周期并产生点时钟同步信号。模拟视频信号通过第一差分缓冲器以产生模拟视频同步信号。模拟视频同步信号通过第一触发器存储元件传送到相位检测器。点时钟同步信号通过第二存储元件，然后通过第二差分缓冲器传送到相位检测器。第二存储缓冲器确保由相位检测器使用的点时钟同步信号的边缘与ADC使用的点时钟信号的采样边紧密连接，以对模拟视频信号中的模拟数据进行采样。此外，第一和第二缓冲器和存储元件将类似的传播时间延迟引入到模拟视频同步信号和点时钟同步信号中。因此，相位检测器精确地比较这些同步信号的相位，并产生用于压控振荡器的高精度电压控制信号，从而产生高精度点时钟信号。

4. 发明授权

US5489946A High speed sync separation system and method 失效
标题翻译：高速同步分离系统及方法
公开(公告)号：US5489946A
公开(公告)日：1996-02-06
申请号：US506663
申请日：1995-07-25
申请人： Steven J. Kommrusch , Bradly J. Foster
发明人： Steven J. Kommrusch , Bradly J. Foster
IPC分类号： H04N5/08 , H04N5/06
CPC分类号： H04N5/08
摘要： A synchronization (sync) separation system and method quickly and accurately generate a sync signal from an analog video signal by using feedback control. The system comprises a voltage generator for generating first and second reference voltages V.sub.REF1, V.sub.REF2. A first comparator compares the analog video signal to the first reference voltage V.sub.REF1 and generates a shift control signal, A voltage shift mechanism receives the shift control signal and adjusts the analog video signal so that the sync level of the analog video signal converges toward the first reference voltage V.sub.REF1. A second comparator compares the analog video signal with the second reference voltage V.sub.REF2 and generates the sync signal indicative of when the analog video signal exhibits the sync level. Preferably, the voltage shift mechanism introduces a continuous current i.sub.c into the analog video signal. Moreover, the second comparator is an ECL differential line receiver in the preferred embodiment for providing a sync signal which is compatible with ECL.
摘要翻译：同步（同步）分离系统和方法通过使用反馈控制快速准确地从模拟视频信号产生同步信号。该系统包括用于产生第一和第二参考电压VREF1，VREF2的电压发生器。第一比较器将模拟视频信号与第一参考电压VREF1进行比较，并生成移位控制信号，电压移位机构接收移位控制信号并调整模拟视频信号，使得模拟视频信号的同步电平朝向第一参考电压VREF1。第二比较器将模拟视频信号与第二参考电压VREF2进行比较，并产生指示何时模拟视频信号表现出同步电平的同步信号。优选地，电压移位机构将连续电流ic引入模拟视频信号。此外，在优选实施例中，第二比较器是ECL差分线路接收机，用于提供与ECL兼容的同步信号。

5. 发明授权

US6052113A Methods and apparatus for processing data values representative of an image with efficient dither matrices 失效
标题翻译：用于处理表示具有高效抖动矩阵的图像的数据值的方法和装置
公开(公告)号：US6052113A
公开(公告)日：2000-04-18
申请号：US865755
申请日：1997-05-30
申请人： Bradly J. Foster
发明人： Bradly J. Foster
IPC分类号： G09G3/20 , G09G5/37 , G09G5/39 , H04N1/405 , H04N1/52 , G09G5/10
CPC分类号： H04N1/52 , G09G5/39 , H04N1/4051 , G09G3/2051
摘要： Data values representative of a source image are processed with a dither matrix having dither values corresponding to pixel locations in the source image. The dither matrix has dimensions n.times.n, where n is modulo 4 and an integer value m exists such that m.multidot.m=n. The dither matrix is typically a 4.times.4 matrix. The dither values are arranged in the dither matrix such that each row, column, diagonal and m.times.m submatrix in the dither matrix adds to substantially the same value, preferably the sum of all dither values in the dither matrix divided by n. A dither value corresponding to a pixel location is accessed in the dither matrix. An initial data value associated with the pixel location is combined with the accessed dither value, typically by adding, to provide an intermediate value. The intermediate value is clamped and truncated to provide a dithered data value. Where each pixel is represented by two or more data values, such as color values, a dither matrix is associated with each parameter. Preferably, the sum of the selected dither matrices is a matrix having matrix values that are substantially the same.
摘要翻译：使用具有与源图像中的像素位置对应的抖动值的抖动矩阵来处理表示源图像的数据值。抖动矩阵的维数为nxn，其中n为模4，存在整数值m，使得mxm = n。抖动矩阵通常是4×4矩阵。抖动值被布置在抖动矩阵中，使得抖动矩阵中的每个行，列，对角线和m×m子矩阵添加到基本上相同的值，优选地将抖动矩阵中的所有抖动值的和除以n。在抖动矩阵中访问对应于像素位置的抖动值。与像素位置相关联的初始数据值与所访问的抖动值组合，通常通过加法来提供中间值。中间值被钳位并截断以提供抖动的数据值。在每个像素由两个或多个数据值（例如颜色值）表示的情况下，抖动矩阵与每个参数相关联。优选地，所选择的抖动矩阵的和是具有基本相同的矩阵值的矩阵。

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