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1. 发明授权

US5446496A Frame rate conversion with asynchronous pixel clocks 失效
标题翻译：具有异步像素时钟的帧速率转换
公开(公告)号：US5446496A
公开(公告)日：1995-08-29
申请号：US221433
申请日：1994-03-31
申请人： Bradly J. Foster , David J. Hodge , Steven J. Kommrusch
发明人： Bradly J. Foster , David J. Hodge , Steven J. Kommrusch
IPC分类号： H04N5/04 , G09G3/20 , G09G5/00 , G09G5/39 , H04N7/01 , H04N9/64
CPC分类号： G09G5/005 , G09G5/39 , H04N7/01 , H04N7/0105 , G09G2340/0435 , G09G2360/18 , G09G5/006
摘要： A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control. Moreover, the display control synchronizes the writing and reading operations by the frame buffer control and the display control, respectively, each time that a frame has been skipped. Furthermore, the frame buffer control causes the VRAM frame buffer to transfer data from the split memory to the shift register when the horizontal blank is deasserted within the incoming analog video signal.
摘要翻译：帧速率转换系统将数据传输与来自并发，连续和异步的VRAM帧缓冲器进行同步。该系统包括具有用于将数据传送到分离输出移位寄存器的分离存储器的帧缓冲器。帧缓冲器控制以第一帧速率监视对分离存储器的写入操作。显示控制器以比第一帧速率慢的第二帧速率监视来自移位寄存器的读取操作。帧缓冲器控制和显示控制通过双同步器传送控制信号。显示控制具有用于计数从VRAM帧缓冲器读取的数据帧的计数器。显示控制防止在特定数量的帧被计数之后将帧写入分离存储器，以防止帧缓冲器控制通过显示器写入并破坏尚未从分离存储器读取的现有数据控制。此外，每当帧被跳过时，显示控制分别通过帧缓冲器控制和显示控制来同步写入和读取操作。此外，当输入模拟视频信号中的空白被取消置位时，帧缓冲器控制使得VRAM帧缓冲器将数据从分离存储器传送到移位寄存器。

2. 发明授权

US5293593A Method and apparatus for the mapping of physically non-contiguous memory fragments to be linearly addressable 失效
标题翻译：用于将物理上非连续的存储器片段映射成可线性寻址的方法和装置
公开(公告)号：US5293593A
公开(公告)日：1994-03-08
申请号：US596176
申请日：1990-10-11
申请人： David J. Hodge , John C. Keith , Lief J. Sorensen , Steven P. Tucker
发明人： David J. Hodge , John C. Keith , Lief J. Sorensen , Steven P. Tucker
IPC分类号： G06F12/02 , G06T1/60 , G09G5/39
CPC分类号： G09G5/39
摘要： A method and apparatus for use in read/write operations by a processor that reads and writes information in first and second address formats. The method and apparatus include a memory and a memory mapper for remapping according to a predetermined scheme those memory fragments not containing information stored in the first address format. Memory fragments are thus accessible to the processor for reading and writing information in the second address format. Such remapping operation results in the memory fragments appearing logically contiguous. In the preferred embodiment, the first address format is an x-y address format and the second address format is a linearly addressable format. An alternative embodiment discloses the use of a second memory for reading and writing information in the second address format. In that embodiment, the memory mapper remaps the memory fragments to appear logically contiguous with said second memory. The invention finds particular utility in conjunction with a graphics processor system. In such a system, the memory mapper is a programmable array logic device and the memory is VRAM memory. In certain situations it is preferred to remap that portion of the memory where information is to be stored in the first address format so that the first information signal is stored in locations which are physically contiguous.
摘要翻译：一种用于以第一和第二地址格式读取和写入信息的处理器在读/写操作中使用的方法和装置。该方法和装置包括存储器和用于根据预定方案重新映射的存储器映射器，这些存储器片段不包含以第一地址格式存储的信息。因此，存储器片段可由处理器访问，用于以第二地址格式读取和写入信息。这种重映射操作导致存储器片段看起来逻辑上相邻。在优选实施例中，第一地址格式是x-y地址格式，第二地址格式是线性可寻址格式。替代实施例公开了使用第二存储器来读取和写入第二地址格式的信息。在该实施例中，存储器映射器重新映射存储器片段以与所述第二存储器逻辑地邻接。本发明结合图形处理器系统特别实用。在这样的系统中，存储器映射器是可编程阵列逻辑器件，存储器是VRAM存储器。在某些情况下，优选地以第一地址格式重新映射要存储信息的存储器的那部分，使得第一信息信号被存储在物理上相邻的位置。

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