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1. 发明授权

US06437781B1 Computer graphics system having per pixel fog blending 失效
公开(公告)号：US06437781B1
公开(公告)日：2002-08-20
申请号：US08866556
申请日：1997-05-30
申请人： S. Paul Tucker , Bradly J. Foster , Steven J. Kommrusch
发明人： S. Paul Tucker , Bradly J. Foster , Steven J. Kommrusch
IPC分类号： G06T1550
CPC分类号： G06T15/503
摘要： A computer graphics system includes an apparatus for fog blending colors to be displayed on a graphics display of the computer graphics system. The computer graphics system includes a rendering parameter calculation unit responsive to data of a primitive, that determines a cooked exponent value and a color value for at least one pixel of the primitive. In addition, the system includes a fog unit responsive to the cooked exponent value for each pixel of the primitive, that determines a fog blending factor for each pixel of the primitive, wherein the fog blending factor is one of an exponential fog blending factor and an exponential-squared fog blending factor. Further, the system includes a fog blending unit responsive to the color value and the fog blending factor for each pixel of the primitive and also to a fog color value, that blends the fog color value with the color value for each pixel of the primitive according to the fog blending factor for the respective pixel, and that provides a fogged color value for each pixel of the primitive. In addition, the computer graphics system may include a first interpolator, responsive to the color value and the cooked exponent value for at least one pixel of the primitive, that determines the color value and the cooked exponent value along an edge of the primitive so as to provide the cooked exponent value and the color value for each pixel of the edge of the primitive. Further, the computer graphics system may also include a second interpolator, responsive to the cooked exponent value and the color value for each pixel of the edge of the primitive, that determines the cooked exponent value and the color value along a span of the primitive so as to provide the cooked exponent value and the color value for each pixel of the span of the primitive. In this way, the system provides fast and accurate exponential and exponential-squared fog blending of the color values of the primitive without a lot of hardware.

2. 发明授权

US06219071B1 ROM-based control unit in a geometry accelerator for a computer graphics system 有权
标题翻译：用于计算机图形系统的几何加速器中基于ROM的控制单元
公开(公告)号：US06219071B1
公开(公告)日：2001-04-17
申请号：US09209934
申请日：1998-10-06
申请人： Alan S. Krech, Jr. , Theodore G. Rossin , Edmundo Rojas , Michael S McGrath , Ted Rakel , Glenn W Strunk , Jon L Ashburn , S Paul Tucker
发明人： Alan S. Krech, Jr. , Theodore G. Rossin , Edmundo Rojas , Michael S McGrath , Ted Rakel , Glenn W Strunk , Jon L Ashburn , S Paul Tucker
IPC分类号： G06F1516
CPC分类号： G06T1/20
摘要： The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.
摘要翻译：本发明提供了一种用于使计算机图形系统的几何加速器中的空间需求最小化并提高速度的系统和方法。在架构中，系统实现如下。几何加速器包括多个处理元件（例如，算术逻辑单元，乘法器，分频器，比较机构，钳位机构等）和多个控制单元（例如，变换机构，分解机构，夹子机构，蝴蝶结机构，光机构，分类机构，平面方程机构，雾化机构等），其利用处理元件对图像数据进行数据处理。根据本发明，控制单元通过微代码实现在只读存储器（ROM）中。下一个地址字段与每个微代码指令相关联，并定义ROM中要执行的下一条指令的位置。多个控制单元逻辑元件分别对应控制单元和通过定义下一个地址字段在其各自的控制单元内分支的控制指令。分支中央智能机构通过定义下一个地址字段来控制控制单元之间的分支。

3. 发明授权

US5956047A ROM-based control units in a geometry accelerator for a computer graphics system 失效
标题翻译：用于计算机图形系统的几何加速器中基于ROM的控制单元
公开(公告)号：US5956047A
公开(公告)日：1999-09-21
申请号：US846363
申请日：1997-04-30
申请人： Alan S. Krech, Jr. , Theodore G. Rossin , Edmundo Rojas , Michael S McGrath , Ted Rakel , Glenn W Strunk , Jon L Ashburn , S Paul Tucker
发明人： Alan S. Krech, Jr. , Theodore G. Rossin , Edmundo Rojas , Michael S McGrath , Ted Rakel , Glenn W Strunk , Jon L Ashburn , S Paul Tucker
IPC分类号： G06F9/26 , G06T1/20 , G06T11/00 , G06F15/16
CPC分类号： G06T1/20
摘要： The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.
摘要翻译：本发明提供了一种用于使计算机图形系统的几何加速器中的空间要求最小化并提高速度的系统和方法。在架构中，系统实现如下。几何加速器包括多个处理元件（例如，算术逻辑单元，乘法器，分频器，比较机构，钳位机构等）和多个控制单元（例如，变换机构，分解机构，夹子机构，蝴蝶结机构，光机构，分类机构，平面方程机构，雾化机构等），其利用处理元件对图像数据进行数据处理。根据本发明，控制单元通过微代码实现在只读存储器（ROM）中。下一个地址字段与每个微代码指令相关联，并定义ROM中要执行的下一条指令的位置。多个控制单元逻辑元件分别对应控制单元和通过定义下一个地址字段在其各自的控制单元内分支的控制指令。分支中央智能机构通过定义下一个地址字段来控制控制单元之间的分支。

4. 发明授权

US07209478B2 Apparatus and methods for dynamic reallocation of virtual lane buffer space in an infiniband switch 有权
标题翻译：虚拟通道缓冲区空间动态重新分配的设备和方法
公开(公告)号：US07209478B2
公开(公告)日：2007-04-24
申请号：US10160938
申请日：2002-05-31
申请人： Edmundo Rojas , S. Paul Tucker
发明人： Edmundo Rojas , S. Paul Tucker
IPC分类号： H04L12/50
CPC分类号： H04L49/25 , H04L49/101 , H04L49/201 , H04L49/254 , H04L49/3018 , H04L49/358 , H04L49/90
摘要： A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet-based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar using a variable number of virtual lanes. A state machine controls the changing of the number of virtual lanes.
摘要翻译：用于InfiniBand网络的交换机。交换机包括基于转发表重定向基于分组的数据的交叉开关。至少一个端口从网络接收数据，并使用可变数量的虚拟通道选择性地将数据传输到交叉开关。状态机控制虚拟车道数量的变化。

5. 发明授权

US06898752B2 Apparatus and methods for combinational error detection in an InfiniBand switch 失效
标题翻译： InfiniBand交换机中组合错误检测的装置和方法
公开(公告)号：US06898752B2
公开(公告)日：2005-05-24
申请号：US10161503
申请日：2002-05-31
申请人： S. Paul Tucker
发明人： S. Paul Tucker
IPC分类号： H03M13/00 , H03M13/09
CPC分类号： H03M13/09 , H03M13/00
摘要： A combination error detector to detect errors in an InfiniBand packet. The detector includes registers that stores fields of an InfiniBand packet as the packet is being received and comparison logic that, as the fields are stored in the registers, compares the fields with check values and when an error is detected sets a flag corresponding to the error. After the packet has been completely received and all checks have been complete, all of the error flags are prioritized in accordance with the InfiniBand Architecture Specification.
摘要翻译：用于检测InfiniBand数据包中的错误的组合错误检测器。检测器包括在接收到数据包时存储InfiniBand数据包的字段的寄存器，以及比较逻辑，当字段存储在寄存器中时，将字段与检查值进行比较，并且当检测到错误时，设置与错误对应的标志。在数据包已经完全接收并且所有检查都已经完成之后，根据InfiniBand架构规范对所有错误标志进行优先级排序。

6. 发明授权

US07184411B2 Switch-management agent trap scheme in an infiniband-architecture switch 有权
标题翻译：无源架构交换机中的交换机管理代理陷阱方案
公开(公告)号：US07184411B2
公开(公告)日：2007-02-27
申请号：US10321233
申请日：2002-12-17
申请人： S. Paul Tucker , Venitha L Manter
发明人： S. Paul Tucker , Venitha L Manter
IPC分类号： H04L1/16 , H04L3/14 , H04L12/56 , H04L12/28 , H03M13/00
CPC分类号： H04L41/0604 , H04L41/046
摘要： An infiniband architecture switch, includes a plurality of ports each configured to receive switch parameters, identify at least one data-packet error condition responsive to the switch parameters, generate a trap-initialization signal when the at least one data-packet error condition matches a trap-error condition, and a switch manager configured to receive the trap-initialization signal. A method for generating a switch manager control signal includes identifying at least one data-packet error condition in an infiniband architecture switch, determining when the at least one data-packet error condition matches a trap-error condition, generating a trap-initialization signal responsive to the trap-error condition, and forwarding the trap-initialization signal to a switch manager.
摘要翻译：无限性架构交换机包括多个端口，每个端口被配置为接收开关参数，响应于该开关参数识别至少一个数据分组错误状况，当至少一个数据分组错误条件匹配时产生一个陷阱初始化信号陷阱错误条件，以及配置为接收陷阱初始化信号的交换机管理器。一种用于产生交换管理器控制信号的方法包括识别无限制架构交换机中的至少一个数据分组错误状况，确定何时至少一个数据分组错误状况与陷阱误差条件相匹配，产生响应于陷阱初始化信号到陷阱错误状态，并将陷阱初始化信号转发给交换机管理器。

7. 发明授权

US06919898B2 Method and apparatus for ascertaining and selectively requesting displayed data in a computer graphics system 有权
标题翻译：用于在计算机图形系统中确定和选择性地请求显示数据的方法和装置
公开(公告)号：US06919898B2
公开(公告)日：2005-07-19
申请号：US09488752
申请日：2000-01-21
申请人： S. Paul Tucker , Kyle R. Berry
发明人： S. Paul Tucker , Kyle R. Berry
IPC分类号： G09G5/30 , G09G5/395 , G06T15/00
CPC分类号： G09G5/30 , G09G5/395
摘要： Regions of frame buffer memory are selectively read by a computer graphics system in a bandwidth efficient manor. Attribute data for each pixel is stored in the frame buffer memory array. This attribute data, when decoded, selects which regions of frame buffer memory are required for display of each pixel. Pixels are grouped as tiles. Before each tile is displayed, attribute data is read for that tile, then decoded, and the frame buffer memory is accessed only for those regions that are needed to display the current tile of pixels.
摘要翻译：帧缓冲存储器的区域由带宽有效的庄园中的计算机图形系统选择性地读取。每个像素的属性数据存储在帧缓冲存储器阵列中。该属性数据在被解码时选择需要帧缓冲存储器的哪个区域来显示每个像素。像素被分组为瓦片。在显示每个瓦片之前，为该瓦片读取属性数据，然后解码，并且仅对需要显示当前像素图块的那些区域访问帧缓冲存储器。

8. 发明授权

US5956042A Graphics accelerator with improved lighting processor 失效
标题翻译：具有改进照明处理器的图形加速器
公开(公告)号：US5956042A
公开(公告)日：1999-09-21
申请号：US846364
申请日：1997-04-30
申请人： S Paul Tucker , Alan S. Krech, Jr.
发明人： S Paul Tucker , Alan S. Krech, Jr.
IPC分类号： G06T1/20 , G06F15/00
CPC分类号： G06T1/20
摘要： A system and method computes the color of a plurality of vertices of one or more graphic primitives in a graphics accelerator. The method includes the steps of receiving lighting properties of a primitive vertex and determining whether predetermined lighting properties of the vertex are the same as a previously computed vertex. If predetermined lighting properties are the same as the previously computed vertex, then the method retrieves at least one preprocessed value from a storage location; and utilizes the at least one preprocessed value to compute the vertex color. If, however, the predetermined lighting properties are not the same as the previously computed vertex, then the method computes at least one preprocessed value from the received lighting properties of the primitive vertex, stores the at least one computed preprocessed value in a storage location, and utilizes the at least one preprocessed value to compute the vertex color. The system includes at least one processing unit (e.g., ALU) for performing mathematical operations on lighting properties of a vertex of a graphics primitive. It also includes a storage area for storing predetermined values processed by the processing unit. A receiver is included and configured to receive at least two lighting properties defining a primitive vertex, and a lighting property comparator is configured to compare the at least two lighting properties with previously received lighting properties to determine whether they are the same. Finally a controller is provided and adapted to control the storage and retrieval of values from the storage area and the processing unit, the controller including storage control means responsive to the lighting property comparator configured to save newly processed vertex color values in the operational storage register and to retrieve preprocessed values from the storage area.
摘要翻译：系统和方法计算图形加速器中的一个或多个图形基元的多个顶点的颜色。该方法包括以下步骤：接收原始顶点的照明属性并确定顶点的预定照明属性是否与先前计算的顶点相同。如果预定的照明属性与先前计算的顶点相同，则该方法从存储位置检索至少一个预处理值; 并利用至少一个预处理值来计算顶点颜色。然而，如果预定的照明属性与先前计算的顶点不同，则该方法根据接收到的原始顶点的照明属性来计算至少一个预处理值，将至少一个计算的预处理值存储在存储位置中，并利用至少一个预处理值来计算顶点颜色。该系统包括用于对图形原语的顶点的照明属性执行数学运算的至少一个处理单元（例如，ALU）。它还包括用于存储由处理单元处理的预定值的存储区域。接收器被包括并被配置为接收定义原始顶点的至少两个照明属性，并且照明属性比较器被配置为将至少两个照明属性与先前接收的照明属性进行比较，以确定它们是否相同。最后，提供控制器，用于控制来自存储区域和处理单元的值的存储和检索，控制器包括存储控制装置，其响应于照明属性比较器被配置为将新处理的顶点颜色值保存在操作存储寄存器中，以及从存储区域检索预处理值。

9. 发明授权

US5912830A System and method for conditionally calculating exponential values in a geometry accelerator 失效
标题翻译：用于有条件地计算几何加速器中的指数值的系统和方法
公开(公告)号：US5912830A
公开(公告)日：1999-06-15
申请号：US846365
申请日：1997-04-30
申请人： Alan S. Krech, Jr. , S Paul Tucker
发明人： Alan S. Krech, Jr. , S Paul Tucker
IPC分类号： G06F7/556 , G06F7/38
CPC分类号： G06F7/556
摘要： A method computes exponentials of a lighting equation in a geometry accelerator. In accordance with one aspect of the invention, the method includes the steps of receiving values for a first term "a" and a second term "x" of an exponential in the form a.sup.x. The method then evaluates at least one of the first and second terms to determine whether it is an integer value. If the evaluating step determines that the at least one of the terms is an integer value, then the method sets a bit in a memory location. Thereafter, the method examines a bit in the memory location. If the bit is set, then the invention executes an integer exponentiation routine to calculate a.sup.x directly in the math core. If, however, the bit is not set, then the invention executes a floating point exponentiation routine to closely approximate the calculation of a.sup.x.
摘要翻译：一种方法计算几何加速器中的照明方程式的指数。根据本发明的一个方面，该方法包括以下形式的步骤：接收角度为ax的指数的第一项“a”和第二项“x”的值。该方法然后评估第一和第二项中的至少一个以确定其是否是整数值。如果评估步骤确定该项中的至少一个是整数值，则该方法在存储器位置中设置一位。此后，该方法检查存储器位置中的一点。如果该位被置位，则本发明执行整数乘幂程序以在数学核心中直接计算ax。然而，如果该位未设置，则本发明执行浮点乘幂程序以紧密地计算ax的计算。

10. 发明授权

US07315542B2 Handling and discarding packets in a switching subnetwork 有权
标题翻译：处理和丢弃交换子网中的数据包
公开(公告)号：US07315542B2
公开(公告)日：2008-01-01
申请号：US10261012
申请日：2002-09-30
申请人： Mercedes E Gil , S. Paul Tucker , Edmundo Rojas
发明人： Mercedes E Gil , S. Paul Tucker , Edmundo Rojas
IPC分类号： H04L12/28 , H04L1/18
CPC分类号： H04L47/10 , H04L29/06 , H04L47/32 , H04L69/22
摘要： A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory. The packet transfer request generator initiates a transfer request over a switch with a remote destination. While the request is processed, the packet checker verifies packet correctness and stores the packet data for transmission to the remote destination. If a packet is in error, a bad tag is set and the packet transfer is aborted.
摘要翻译：用于处理和丢弃分组数据网络中的分组的方法和结构。该方法包括分组数据网络，从一个或多个远程位置接收一个或多个分组，并且发起一个或多个分组的分组到远程目的地的传送。远程目的地可用作交换机的目的端口。在接收到一个或多个分组的分组时启动分组的传送，并且在分组的传输被启动时也检查分组有效性。如果分组无效，则将一个或多个分组的分组传送到远程目的地被取消。确定包的有效性包括对包头的检查。该结构具有确定分组有效性的接收链路，并将该错误信号传递给分组处理器。分组处理器具有分组传输请求生成器，分组检查器，分组读取器，分组存储器和标签存储器。分组传输请求生成器通过具有远程目的地的交换机发起传送请求。当请求被处理时，分组检查器验证分组的正确性并存储分组数据以传输到远程目的地。如果一个数据包出错，则会设置一个错误的标签，并且中继传输数据包。

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