专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070067612A1 Arithmetic operation apparatus, information processing apparatus, and register file control method 失效
标题翻译：算术运算装置，信息处理装置和寄存器文件控制方法
公开(公告)号：US20070067612A1
公开(公告)日：2007-03-22
申请号：US11333229
申请日：2006-01-18
申请人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
发明人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
IPC分类号： G06F9/44
CPC分类号： G06F9/30043 , G06F9/30127 , G06F9/3851
摘要： The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.
摘要翻译：本装置在采用无序指令执行方法的信息处理装置中减少硬件资源并提高数据读取吞吐量。该装置包括：算术运算单元，执行窗口切换指令和与存储在当前寄存器中的数据或保存在替换缓冲器中的数据有关的指令; 以及控制单元，如果在由算术运算单元执行窗口切换指令时对窗口切换指令进行了解码，则在完成窗口切换的执行完成后由当前窗口指针指定的寄存器窗口的数据指令，到替换缓冲区。

2. 发明授权

US07343478B2 Register window system and method that stores the next register window in a temporary buffer 失效
标题翻译：注册窗口系统和方法将下一个寄存器窗口存储在临时缓冲区中
公开(公告)号：US07343478B2
公开(公告)日：2008-03-11
申请号：US11333229
申请日：2006-01-18
申请人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
发明人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
IPC分类号： G06F9/44
CPC分类号： G06F9/30043 , G06F9/30127 , G06F9/3851
摘要： The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.
摘要翻译：本装置在采用无序指令执行方法的信息处理装置中减少硬件资源并提高数据读取吞吐量。该装置包括：算术运算单元，执行窗口切换指令和与存储在当前寄存器中的数据或保存在替换缓冲器中的数据有关的指令; 以及控制单元，如果在由算术运算单元执行窗口切换指令时对窗口切换指令进行了解码，则在完成窗口切换的执行完成后由当前窗口指针指定的寄存器窗口的数据指令，到替换缓冲区。

3. 发明申请

US20060026470A1 Processor debugging apparatus and processor debugging method 失效
标题翻译：处理器调试设备和处理器调试方法
公开(公告)号：US20060026470A1
公开(公告)日：2006-02-02
申请号：US10986912
申请日：2004-11-15
申请人： Hideo Yamashita , Ryuji Kan
发明人： Hideo Yamashita , Ryuji Kan
IPC分类号： G01R31/28
CPC分类号： G06F11/2236
摘要： A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.
摘要翻译：一种在处理器中扫描和读取锁存器的处理器调试装置，包括：存储处理器中预定信号值多个时钟的寄存器; 以及扫描并读出存储在寄存器中的信号值的信号读取单元。

4. 发明授权

US08015447B2 Processor debugging apparatus and processor debugging method 失效
标题翻译：处理器调试设备和处理器调试方法
公开(公告)号：US08015447B2
公开(公告)日：2011-09-06
申请号：US10986912
申请日：2004-11-15
申请人： Hideo Yamashita , Ryuji Kan
发明人： Hideo Yamashita , Ryuji Kan
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.
摘要翻译：一种在处理器中扫描和读取锁存器的处理器调试装置，包括：存储处理器中预定信号值多个时钟的寄存器; 以及扫描并读出存储在寄存器中的信号值的信号读取单元。

5. 发明申请

US20080172551A1 OPERATION VERIFICATION METHOD FOR VERIFYING OPERATIONS OF A PROCESSOR 审中-公开
标题翻译：用于验证处理器操作的操作验证方法
公开(公告)号：US20080172551A1
公开(公告)日：2008-07-17
申请号：US12028371
申请日：2008-02-08
申请人： Hideo YAMASHITA , Ryuji Kan
发明人： Hideo YAMASHITA , Ryuji Kan
IPC分类号： G06F9/30
CPC分类号： G06F11/2226
摘要： To verify an addition-function of a floating-point adder-subtractor in a processor, parameters such as the number of verification patterns of a verification program are set, a floating-point addition instruction to be verified is created, and operands used for this addition are created at random. The floating-point addition instruction thus created is emulated only by a fixed-point instruction and processed only by using the fixed-point execution element, thereby creating an expectation value. The floating-point addition instruction is computed by using the floating-point adder-subtractor to be verified, and the created expectation value is compared with the operation result. If they do not correspond to each other, the set number of operation patterns is checked. If the number has reached a prescribed value, the operation verification is terminated in the normal manner.
摘要翻译：为了验证处理器中的浮点加减法器的附加功能，设置诸如验证程序的验证模式数的参数，创建要验证的浮点加法指令，并且为此使用操作数随机创建添加。这样创建的浮点附加指令仅由定点指令进行仿真，并且仅通过使用定点执行元件进行处理，从而创建期望值。通过使用要验证的浮点加法器 - 减法器来计算浮点加法指令，并将创建的期望值与运算结果进行比较。如果它们不对应，则检查设定的操作模式数。如果数量达到规定值，则以正常的方式终止运行验证。

6. 发明申请

US20100095103A1 Instruction execution control device and instruction execution control method 失效
标题翻译：指令执行控制装置和指令执行控制方法
公开(公告)号：US20100095103A1
公开(公告)日：2010-04-15
申请号：US12591993
申请日：2009-12-07
申请人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
发明人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/30127 , G06F9/30141
摘要： An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.
摘要翻译：指令执行控制装置在同时多线程系统中操作多个线程。该装置具有针对每个线程的架构寄存器（22-0,22-1）和选择电路（32,24），当从寄存器文件（20）读取执行功能所需的操作数数据时，选择推进从注册文件（20）读取的线程。这使得能够在早期阶段选择体系结构寄存器，并且尽管用于选择架构寄存器的部分中的电路数量增加，但是由于要读取的线程的体系结构寄存器可以减少电路的布线量提前选择。

7. 发明授权

US08655935B2 Processing apparatus and control method performing taylor series operation associated with executing floating point instruction 有权
标题翻译：执行与执行浮点指令相关的泰勒系列操作的处理装置和控制方法
公开(公告)号：US08655935B2
公开(公告)日：2014-02-18
申请号：US12047782
申请日：2008-03-13
申请人： Mikio Hondou , Ryuji Kan , Toshio Yoshida
发明人： Mikio Hondou , Ryuji Kan , Toshio Yoshida
IPC分类号： G06F1/02
CPC分类号： G06F7/548 , G06F1/02 , G06F7/483 , G06F7/5443
摘要： A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.
摘要翻译：一种处理装置，包括存储操作数数据的寄存器，读取存储在寄存器中的操作数数据的寄存器数据读取部，存储存储泰勒级数运算系数数据的系数表的系数表组存储部，读取使用泰勒级数的度数信息和系数表识别信息的系数表组存储部分的泰勒级数系数数据和使用由系数数据读取部分读取的系数数据执行泰勒级数操作的浮点乘法器，从寄存器读取的数据。

8. 发明授权

US07958338B2 Instruction execution control device and instruction execution control method 失效
标题翻译：指令执行控制装置和指令执行控制方法
公开(公告)号：US07958338B2
公开(公告)日：2011-06-07
申请号：US12591993
申请日：2009-12-07
申请人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
发明人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
IPC分类号： G06F9/38 , G06F9/52
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/30127 , G06F9/30141
摘要： An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.
摘要翻译：指令执行控制装置在同时多线程系统中操作多个线程。该装置具有针对每个线程的架构寄存器（22-0,22-1）和选择电路（32,24），当从寄存器文件（20）读取执行功能所需的操作数数据时，选择推进从注册文件（20）读取的线程。这使得能够在早期阶段选择体系结构寄存器，并且尽管用于选择架构寄存器的部分中的电路数量增加，但是由于要读取的线程的体系结构寄存器可以减少电路的布线量提前选择。

9. 发明申请

US20080228846A1 PROCESSING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：处理装置及其控制方法
公开(公告)号：US20080228846A1
公开(公告)日：2008-09-18
申请号：US12047782
申请日：2008-03-13
申请人： Mikio HONDOU , Ryuji Kan , Toshio Yoshida
发明人： Mikio HONDOU , Ryuji Kan , Toshio Yoshida
IPC分类号： G06F7/483
CPC分类号： G06F7/548 , G06F1/02 , G06F7/483 , G06F7/5443
摘要： A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.
摘要翻译：一种处理装置，包括存储操作数数据的寄存器，读取存储在寄存器中的操作数数据的寄存器数据读取部分，存储存储泰勒级数运算系数数据的系数表的系数表存储部分，读取使用泰勒级数的度数信息和系数表识别信息的系数表组存储部分的泰勒级数系数数据和使用由系数数据读取部分读取的系数数据执行泰勒级数操作的浮点乘法器，从寄存器读取的数据。

10. 发明授权

US08549054B2 Arithmetic processing apparatus and arithmetic processing method 失效
标题翻译：算术处理装置和算术处理方法
公开(公告)号：US08549054B2
公开(公告)日：2013-10-01
申请号：US12230029
申请日：2008-08-21
申请人： Ryuji Kan
发明人： Ryuji Kan
IPC分类号： G06F7/00 , G06F7/42
CPC分类号： G06F7/38
摘要： In an arithmetic processing apparatus, a dividing unit divides a second bit string into a low-order bit part having a bit width equal to a first bit width and a high-order bit part which is higher than the low-order bit part, a first arithmetic unit performs arithmetic operations for a carry to and a borrow from the high-order bit part; and a second arithmetic unit performs addition of absolute values of the low-order bit part and the first bit string. Finally, a selecting unit selects an output of the first arithmetic unit from among an arithmetic operation result with a carry, an arithmetic operation result with a borrow, and the high-order bit part itself, according to information about the high-order bit part, sign information of the first bit string and the second bit string, and an intermediate result of the addition of the absolute values by the second arithmetic unit.
摘要翻译：在算术处理装置中，分割单元将第二比特串分为具有等于第一比特宽度的比特宽度的低位比特部分和高于低位比特部分的高位比特部分，第一算术单元对从高位位进行进位和借位执行算术运算; 并且第二运算单元执行所述低位位部分和所述第一位串的绝对值的相加。最后，选择单元根据有关高位位部分的信息，从具有进位的算术运算结果，借位运算结果和高阶位部分本身中选择第一算术单元的输出，第一位串和第二位串的符号信息，以及由第二运算单元添加绝对值的中间结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式