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1. 发明授权

US08655935B2 Processing apparatus and control method performing taylor series operation associated with executing floating point instruction 有权
标题翻译：执行与执行浮点指令相关的泰勒系列操作的处理装置和控制方法
公开(公告)号：US08655935B2
公开(公告)日：2014-02-18
申请号：US12047782
申请日：2008-03-13
申请人： Mikio Hondou , Ryuji Kan , Toshio Yoshida
发明人： Mikio Hondou , Ryuji Kan , Toshio Yoshida
IPC分类号： G06F1/02
CPC分类号： G06F7/548 , G06F1/02 , G06F7/483 , G06F7/5443
摘要： A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.
摘要翻译：一种处理装置，包括存储操作数数据的寄存器，读取存储在寄存器中的操作数数据的寄存器数据读取部，存储存储泰勒级数运算系数数据的系数表的系数表组存储部，读取使用泰勒级数的度数信息和系数表识别信息的系数表组存储部分的泰勒级数系数数据和使用由系数数据读取部分读取的系数数据执行泰勒级数操作的浮点乘法器，从寄存器读取的数据。

2. 发明申请

US20080228846A1 PROCESSING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：处理装置及其控制方法
公开(公告)号：US20080228846A1
公开(公告)日：2008-09-18
申请号：US12047782
申请日：2008-03-13
申请人： Mikio HONDOU , Ryuji Kan , Toshio Yoshida
发明人： Mikio HONDOU , Ryuji Kan , Toshio Yoshida
IPC分类号： G06F7/483
CPC分类号： G06F7/548 , G06F1/02 , G06F7/483 , G06F7/5443
摘要： A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.
摘要翻译：一种处理装置，包括存储操作数数据的寄存器，读取存储在寄存器中的操作数数据的寄存器数据读取部分，存储存储泰勒级数运算系数数据的系数表的系数表存储部分，读取使用泰勒级数的度数信息和系数表识别信息的系数表组存储部分的泰勒级数系数数据和使用由系数数据读取部分读取的系数数据执行泰勒级数操作的浮点乘法器，从寄存器读取的数据。

3. 发明授权

US08281112B2 Processor decoding extension instruction to store plural address extension information in extension register for plural subsequent instructions 有权
标题翻译：处理器解码扩展指令，用于在多个后续指令的扩展寄存器中存储多个地址扩展信息
公开(公告)号：US08281112B2
公开(公告)日：2012-10-02
申请号：US12338245
申请日：2008-12-18
申请人： Toshio Yoshida , Mikio Hondou
发明人： Toshio Yoshida , Mikio Hondou
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/30101
摘要： A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.
摘要翻译：处理单元具有扩展寄存器，可以设置指示扩展指令的指令扩展信息。一种操作单元，当指令扩展信息被设置为扩展寄存器时，执行将指令扩展信息写入扩展寄存器的第一指令之后的后续指令，根据指令扩展信息来扩展后续指令。

4. 发明申请

US20090172367A1 PROCESSING UNIT 有权
标题翻译：处理单元
公开(公告)号：US20090172367A1
公开(公告)日：2009-07-02
申请号：US12338245
申请日：2008-12-18
申请人： Toshio Yoshida , Mikio Hondou
发明人： Toshio Yoshida , Mikio Hondou
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/30101
摘要： A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.
摘要翻译：处理单元具有扩展寄存器，可以设置指示扩展指令的指令扩展信息。一种操作单元，当指令扩展信息被设置为扩展寄存器时，执行将指令扩展信息写入扩展寄存器的第一指令之后的后续指令，根据指令扩展信息来扩展后续指令。

5. 发明授权

US08583872B2 Cache memory having sector function 有权
标题翻译：具有扇区功能的缓存存储器
公开(公告)号：US08583872B2
公开(公告)日：2013-11-12
申请号：US12193888
申请日：2008-08-19
申请人： Shuji Yamamura , Mikio Hondou , Iwao Yamazaki , Toshio Yoshida
发明人： Shuji Yamamura , Mikio Hondou , Iwao Yamazaki , Toshio Yoshida
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/127
摘要： A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.
摘要翻译：具有根据设定的关联系统操作的扇区功能的高速缓存存储器，并且执行高速缓存操作以以与在发生高速缓存未命中时确定的替换高速缓存方式相对应的高速缓存方式来替换高速缓存块中的数据包括：存储与由存储器访问请求指定的高速缓存块中的每个缓存路径相关联的扇区ID信息; 根据附加到存储器访问请求的扇区ID信息和存储的扇区ID信息，确定高速缓存未命中的替换方式候选; 从替代方式候选人中选择和输出替代方式; 以及将与由存储器访问请求指定的高速缓存块中的每个高速缓存路径相关联地存储的扇区ID信息更新到附加到存储器访问请求的扇区ID信息。

6. 发明授权

US07958338B2 Instruction execution control device and instruction execution control method 失效
标题翻译：指令执行控制装置和指令执行控制方法
公开(公告)号：US07958338B2
公开(公告)日：2011-06-07
申请号：US12591993
申请日：2009-12-07
申请人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
发明人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
IPC分类号： G06F9/38 , G06F9/52
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/30127 , G06F9/30141
摘要： An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.
摘要翻译：指令执行控制装置在同时多线程系统中操作多个线程。该装置具有针对每个线程的架构寄存器（22-0,22-1）和选择电路（32,24），当从寄存器文件（20）读取执行功能所需的操作数数据时，选择推进从注册文件（20）读取的线程。这使得能够在早期阶段选择体系结构寄存器，并且尽管用于选择架构寄存器的部分中的电路数量增加，但是由于要读取的线程的体系结构寄存器可以减少电路的布线量提前选择。

7. 发明授权

US07343478B2 Register window system and method that stores the next register window in a temporary buffer 失效
标题翻译：注册窗口系统和方法将下一个寄存器窗口存储在临时缓冲区中
公开(公告)号：US07343478B2
公开(公告)日：2008-03-11
申请号：US11333229
申请日：2006-01-18
申请人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
发明人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
IPC分类号： G06F9/44
CPC分类号： G06F9/30043 , G06F9/30127 , G06F9/3851
摘要： The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.
摘要翻译：本装置在采用无序指令执行方法的信息处理装置中减少硬件资源并提高数据读取吞吐量。该装置包括：算术运算单元，执行窗口切换指令和与存储在当前寄存器中的数据或保存在替换缓冲器中的数据有关的指令; 以及控制单元，如果在由算术运算单元执行窗口切换指令时对窗口切换指令进行了解码，则在完成窗口切换的执行完成后由当前窗口指针指定的寄存器窗口的数据指令，到替换缓冲区。

8. 发明申请

US20100095103A1 Instruction execution control device and instruction execution control method 失效
标题翻译：指令执行控制装置和指令执行控制方法
公开(公告)号：US20100095103A1
公开(公告)日：2010-04-15
申请号：US12591993
申请日：2009-12-07
申请人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
发明人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/30127 , G06F9/30141
摘要： An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.
摘要翻译：指令执行控制装置在同时多线程系统中操作多个线程。该装置具有针对每个线程的架构寄存器（22-0,22-1）和选择电路（32,24），当从寄存器文件（20）读取执行功能所需的操作数数据时，选择推进从注册文件（20）读取的线程。这使得能够在早期阶段选择体系结构寄存器，并且尽管用于选择架构寄存器的部分中的电路数量增加，但是由于要读取的线程的体系结构寄存器可以减少电路的布线量提前选择。

9. 发明申请

US20070067612A1 Arithmetic operation apparatus, information processing apparatus, and register file control method 失效
标题翻译：算术运算装置，信息处理装置和寄存器文件控制方法
公开(公告)号：US20070067612A1
公开(公告)日：2007-03-22
申请号：US11333229
申请日：2006-01-18
申请人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
发明人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
IPC分类号： G06F9/44
CPC分类号： G06F9/30043 , G06F9/30127 , G06F9/3851
摘要： The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.
摘要翻译：本装置在采用无序指令执行方法的信息处理装置中减少硬件资源并提高数据读取吞吐量。该装置包括：算术运算单元，执行窗口切换指令和与存储在当前寄存器中的数据或保存在替换缓冲器中的数据有关的指令; 以及控制单元，如果在由算术运算单元执行窗口切换指令时对窗口切换指令进行了解码，则在完成窗口切换的执行完成后由当前窗口指针指定的寄存器窗口的数据指令，到替换缓冲区。

10. 发明授权

US08601239B2 Extended register addressing using prefix instruction 有权
标题翻译：使用前缀指令进行扩展寄存器寻址
公开(公告)号：US08601239B2
公开(公告)日：2013-12-03
申请号：US12827238
申请日：2010-06-30
申请人： Toshio Yoshida , Yasunobu Akizuki , Ryuichi Sunayama
发明人： Toshio Yoshida , Yasunobu Akizuki , Ryuichi Sunayama
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30101 , G06F9/30185
摘要： A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction immediately following two instructions of the second prefix instruction, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruction generated by the instruction packing unit.
摘要翻译：处理器包括存储指令的存储单元，包括第一区域和第二区域的指令扩展信息寄存器，指令解码单元，其对包含第一扩展信息的第一前缀指令进行解码，所述第一前缀指令包括第一扩展信息，执行第一前缀指令，并且解码包括第一扩展信息的第二前缀指令和扩展紧跟在第二前缀指令的两个指令之后的指令的第二扩展信息;指令打包单元，其生成包括至少一个第一前缀指令或第二前缀指令的指令，以及当指令解码单元解码第一前缀指令或第二前缀指令时紧跟在第一前缀指令或第二前缀指令之后的指令，执行指令执行单元，剪切由指令包装单元生成的打包指令。

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