专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08621281B2 Information processing apparatus and control method 失效
标题翻译：信息处理装置及控制方法
公开(公告)号：US08621281B2
公开(公告)日：2013-12-31
申请号：US12635896
申请日：2009-12-11
申请人： Ryuji Kan
发明人： Ryuji Kan
IPC分类号： G06F11/00
CPC分类号： G06F11/1064 , G06F9/30105 , G06F9/30127 , G06F9/30138 , G06F9/3865 , G06F11/2215 , G06F11/2236
摘要： A processing apparatus includes: first and second register files, the latter holding a part of data in the former; an operation unit to operate on data in the second register file and to output data; an instruction unit to issue a write instruction to write, to both register files, the output data and an error detection code for it, and first and second occurrence instructions; a first control unit to issue a first generation instruction when receiving the write instruction and the first occurrence instructions; and a first generation unit to generate a first simulated fault data to output it to the first register file when receiving the first generation instruction, and to output the output data and the error detection code to the first register file in absence of the first generation instruction. Similar second control and generation units are also provided mutatis mutandis.
摘要翻译：一种处理装置包括：第一和第二寄存器文件，后者保存前者中的一部分数据; 操作单元，用于对所述第二寄存器堆中的数据进行操作并输出数据; 发出写入指令的指令单元，向两个寄存器文件写入输出数据及其错误检测码，以及第一和第二次发生指令; 第一控制单元，当接收到写入指令和第一次发生指令时发出第一代指令; 以及第一生成单元，用于在接收到第一生成指令时生成第一模拟故障数据以将其输出到第一寄存器文件，并且在没有第一生成指令的情况下将输出数据和错误检测代码输出到第一寄存器堆。相应的第二控制和发电单位也经过必要的修改。

2. 发明申请

US20080320065A1 Arithmetic processing apparatus and arithmetic processing method 失效
标题翻译：算术处理装置和算术处理方法
公开(公告)号：US20080320065A1
公开(公告)日：2008-12-25
申请号：US12230029
申请日：2008-08-21
申请人： Ryuji Kan
发明人： Ryuji Kan
IPC分类号： G06F7/00
CPC分类号： G06F7/38
摘要： In an arithmetic processing apparatus, a dividing unit divides a second bit string into a low-order bit part having a bit width equal to a first bit width and a high-order bit part which is higher than the low-order bit part, a first arithmetic unit performs arithmetic operations for a carry to and a borrow from the high-order bit part; and a second arithmetic unit performs addition of absolute values of the low-order bit part and the first bit string. Finally, a selecting unit selects an output of the first arithmetic unit from among an arithmetic operation result with a carry, an arithmetic operation result with a borrow, and the high-order bit part itself, according to information about the high-order bit part, sign information of the first bit string and the second bit string, and an intermediate result of the addition of the absolute values by the second arithmetic unit.
摘要翻译：在算术处理装置中，分割单元将第二比特串分为具有等于第一比特宽度的比特宽度的低位比特部分和高于低位比特部分的高位比特部分，第一算术单元对从高位位进行进位和借位执行算术运算; 并且第二运算单元执行所述低位位部分和所述第一位串的绝对值的相加。最后，选择单元根据有关高位位部分的信息，从具有进位的算术运算结果，借位运算结果和高阶位部分本身中选择第一算术单元的输出，第一位串和第二位串的符号信息，以及由第二运算单元添加绝对值的中间结果。

3. 发明申请

US20060026470A1 Processor debugging apparatus and processor debugging method 失效
标题翻译：处理器调试设备和处理器调试方法
公开(公告)号：US20060026470A1
公开(公告)日：2006-02-02
申请号：US10986912
申请日：2004-11-15
申请人： Hideo Yamashita , Ryuji Kan
发明人： Hideo Yamashita , Ryuji Kan
IPC分类号： G01R31/28
CPC分类号： G06F11/2236
摘要： A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.
摘要翻译：一种在处理器中扫描和读取锁存器的处理器调试装置，包括：存储处理器中预定信号值多个时钟的寄存器; 以及扫描并读出存储在寄存器中的信号值的信号读取单元。

4. 发明授权

US08549054B2 Arithmetic processing apparatus and arithmetic processing method 失效
标题翻译：算术处理装置和算术处理方法
公开(公告)号：US08549054B2
公开(公告)日：2013-10-01
申请号：US12230029
申请日：2008-08-21
申请人： Ryuji Kan
发明人： Ryuji Kan
IPC分类号： G06F7/00 , G06F7/42
CPC分类号： G06F7/38
摘要： In an arithmetic processing apparatus, a dividing unit divides a second bit string into a low-order bit part having a bit width equal to a first bit width and a high-order bit part which is higher than the low-order bit part, a first arithmetic unit performs arithmetic operations for a carry to and a borrow from the high-order bit part; and a second arithmetic unit performs addition of absolute values of the low-order bit part and the first bit string. Finally, a selecting unit selects an output of the first arithmetic unit from among an arithmetic operation result with a carry, an arithmetic operation result with a borrow, and the high-order bit part itself, according to information about the high-order bit part, sign information of the first bit string and the second bit string, and an intermediate result of the addition of the absolute values by the second arithmetic unit.
摘要翻译：在算术处理装置中，分割单元将第二比特串分为具有等于第一比特宽度的比特宽度的低位比特部分和高于低位比特部分的高位比特部分，第一算术单元对从高位位进行进位和借位执行算术运算; 并且第二运算单元执行所述低位位部分和所述第一位串的绝对值的相加。最后，选择单元根据有关高位位部分的信息，从具有进位的算术运算结果，借位运算结果和高阶位部分本身中选择第一算术单元的输出，第一位串和第二位串的符号信息，以及由第二运算单元添加绝对值的中间结果。

5. 发明申请

US20120259906A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 失效
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259906A1
公开(公告)日：2012-10-11
申请号：US13441020
申请日：2012-04-06
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/483 , G06F7/49942
摘要： An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.
摘要翻译：算术电路计算通过两个值的加减运算获得的并以预定的固定精度表示的值的校正值。

6. 发明申请

US20120259905A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 有权
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259905A1
公开(公告)日：2012-10-11
申请号：US13437969
申请日：2012-04-03
申请人： Ryuji KAN , Hideyuki UNNO , Kenichi Kitamura
发明人： Ryuji KAN , Hideyuki UNNO , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/49942 , G06F7/483
摘要： An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.
摘要翻译：用于量化预量化数据的算术电路包括：第一输入寄存器，用于存储包括尾数和指数的第一格式的预量化数据;存储量化目标指数的第二输入寄存器;指数校正值指示单元指示指数校正值，指数生成单元，用于生成通过从量化目标指数中减去指数校正值而获得的量化指数;移位量生成单元，生成通过减去预量化数据的指数得到的移位量以及来自量化目标指数的指数校正值，用于生成通过将预量化数据的尾数移位由移位量产生单元生成的移位量而获得的量化尾数的移位单元和存储量化数据的输出寄存器其包括由指数生成单元生成的量化指数和量化的尾数gen 由换档单元擦除。

7. 发明申请

US20120259903A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 审中-公开
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259903A1
公开(公告)日：2012-10-11
申请号：US13439932
申请日：2012-04-05
申请人： Ryuji KAN , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji KAN , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/49957
摘要： An arithmetic circuit for rounding pre-rounded data includes a first register to store first-format pre-rounded data that includes a mantissa of a fixed-precision floating-point number using a base-N numbering system, and includes an exponent for the mantissa, a second register to store rounding precision data indicative of precision for rounding the pre-rounded data, a leading zero counting unit to count consecutive zeros starting from a most significant bit of the mantissa stored in the first register, an exponent generating unit to generate a post-round exponent indicative of an exponent for a rounded significant by subtracting the number of zeros counted by the leading zero counting unit and the rounding precision data from a sum of one and the exponent stored in the first register, and an output register to store the post-round exponent and a rounding-add value that is to be added to a digit at which rounding is performed.
摘要翻译：用于舍入前置数据的算术电路包括：第一寄存器，用于存储使用基本N编号系统的包括固定精度浮点数的尾数的第一格式的前置数据，并且包括用于尾数的指数第二寄存器，用于存储指示用于舍入预舍数据的精度的舍入精度数据;前导零计数单元，用于从存储在第一寄存器中的尾数的最高有效位开始计数连续零;指数生成单元，用于生成指示通过从前导零计数单元计数的零的数目和来自存储在第一寄存器中的一个和的指数的舍入精度数据的舍入精度数据来指示舍入有效的指数的后向指数，以及输出寄存器存储后轮指数和要添加到执行舍入的数字的舍入加法值。

8. 发明授权

US08015447B2 Processor debugging apparatus and processor debugging method 失效
标题翻译：处理器调试设备和处理器调试方法
公开(公告)号：US08015447B2
公开(公告)日：2011-09-06
申请号：US10986912
申请日：2004-11-15
申请人： Hideo Yamashita , Ryuji Kan
发明人： Hideo Yamashita , Ryuji Kan
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.
摘要翻译：一种在处理器中扫描和读取锁存器的处理器调试装置，包括：存储处理器中预定信号值多个时钟的寄存器; 以及扫描并读出存储在寄存器中的信号值的信号读取单元。

9. 发明申请

US20100095103A1 Instruction execution control device and instruction execution control method 失效
标题翻译：指令执行控制装置和指令执行控制方法
公开(公告)号：US20100095103A1
公开(公告)日：2010-04-15
申请号：US12591993
申请日：2009-12-07
申请人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
发明人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/30127 , G06F9/30141
摘要： An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.
摘要翻译：指令执行控制装置在同时多线程系统中操作多个线程。该装置具有针对每个线程的架构寄存器（22-0,22-1）和选择电路（32,24），当从寄存器文件（20）读取执行功能所需的操作数数据时，选择推进从注册文件（20）读取的线程。这使得能够在早期阶段选择体系结构寄存器，并且尽管用于选择架构寄存器的部分中的电路数量增加，但是由于要读取的线程的体系结构寄存器可以减少电路的布线量提前选择。

10. 发明申请

US20080172551A1 OPERATION VERIFICATION METHOD FOR VERIFYING OPERATIONS OF A PROCESSOR 审中-公开
标题翻译：用于验证处理器操作的操作验证方法
公开(公告)号：US20080172551A1
公开(公告)日：2008-07-17
申请号：US12028371
申请日：2008-02-08
申请人： Hideo YAMASHITA , Ryuji Kan
发明人： Hideo YAMASHITA , Ryuji Kan
IPC分类号： G06F9/30
CPC分类号： G06F11/2226
摘要： To verify an addition-function of a floating-point adder-subtractor in a processor, parameters such as the number of verification patterns of a verification program are set, a floating-point addition instruction to be verified is created, and operands used for this addition are created at random. The floating-point addition instruction thus created is emulated only by a fixed-point instruction and processed only by using the fixed-point execution element, thereby creating an expectation value. The floating-point addition instruction is computed by using the floating-point adder-subtractor to be verified, and the created expectation value is compared with the operation result. If they do not correspond to each other, the set number of operation patterns is checked. If the number has reached a prescribed value, the operation verification is terminated in the normal manner.
摘要翻译：为了验证处理器中的浮点加减法器的附加功能，设置诸如验证程序的验证模式数的参数，创建要验证的浮点加法指令，并且为此使用操作数随机创建添加。这样创建的浮点附加指令仅由定点指令进行仿真，并且仅通过使用定点执行元件进行处理，从而创建期望值。通过使用要验证的浮点加法器 - 减法器来计算浮点加法指令，并将创建的期望值与运算结果进行比较。如果它们不对应，则检查设定的操作模式数。如果数量达到规定值，则以正常的方式终止运行验证。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式