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    • 3. 发明授权
    • Battery control system and battery pack
    • 电池控制系统和电池组
    • US09525289B2
    • 2016-12-20
    • US14381817
    • 2013-02-08
    • Tadahiro Yoshida
    • Tadahiro Yoshida
    • H02J7/04H02J7/00H02J7/16H01M10/42H01M10/48G01R31/36
    • H02J7/0014G01R31/3606H01M10/425H01M10/482H01M10/486H01M2010/4271H02J7/0016H02J7/0021H02J7/0026H02J7/007H02J7/0091
    • A battery control unit (400) controls charge and discharge of battery cells (100) on the basis of temperatures measured by a temperature measurement unit (320) and voltages measured by the voltage and current measurement unit (340). In addition, the battery control unit (400) specifies a lowest temperature cell having the lowest temperature and a highest temperature cell having the highest temperature on the basis of the temperatures measured by the temperature measurement unit (320), when a current is greater than 0. In addition, the battery control unit (400) performs balance control for equalizing voltages of all the battery cells (100), on the basis of the voltages measured by the voltage and current measurement unit (340), when a first temperature condition in which a temperature difference ΔT between the highest temperature cell and the lowest temperature cell is equal to or greater than a reference value T1 is not satisfied. On the other hand, when the temperature difference ΔT satisfies the first temperature condition, the battery control unit (400) does not perform the balance control.
    • 电池控制单元(400)基于由温度测量单元(320)测量的温度和由电压和电流测量单元(340)测量的电压来控制电池单元(100)的充电和放电。 此外,电池控制单元400根据由温度测量单元320测量的温度,指定具有最低温度的最低温度单元和具有最高温度的最高温度单元,当电流大于 此外,电池控制单元400基于由电压和电流测量单元(340)测量的电压,执行用于均衡所有电池单元(100)的电压的平衡控制,当第一温度条件 其中最高温度单元和最低温度单元之间的温度差ΔT等于或大于参考值T1。 另一方面,当温度差ΔT满足第一温度条件时,电池控制单元(400)不执行平衡控制。
    • 4. 发明申请
    • GAS-INSULATED ELECTRIC DEVICE
    • 气体绝缘电气设备
    • US20130100587A1
    • 2013-04-25
    • US13806202
    • 2010-09-13
    • Tadahiro YoshidaKazuki TakahashiKatsushi NakadaMasahiro Arioka
    • Tadahiro YoshidaKazuki TakahashiKatsushi NakadaMasahiro Arioka
    • H02B13/045
    • H02B13/045H02B1/56H02B13/0358
    • A gas-insulated electric device, by which a cross-sectional area of a central conductor can be reduced. The gas-insulated electric device includes an insulation tube that ranges to portions facing to ground potential portions for a central conductor and to upper-lower portions along the grounding potential portions, and is coaxially arranged along the central conductor in a state where a gap intervenes between the central conductor and the insulation tube; a conductive layer that is formed on an inner surface of an insulation tube and is electrically connected to the central conductor; and a ground layer that is formed on an inner surface or an outer surface of the insulation tube and is grounded; in which heat generated from the central conductor is radiated by convecting the insulation gas through the gap between the central conductor and insulation tube.
    • 一种气体绝缘电气装置,可以减小中心导体的横截面积。 气体绝缘电气装置包括绝缘管,其范围为面向中心导体的地电位部分的部分和沿着接地电位部分的上下部分,并且在间隙干涉的状态下沿着中心导体同轴布置 在中心导体和绝缘管之间; 导电层,其形成在绝缘管的内表面上并与中心导体电连接; 以及形成在绝缘管的内表面或外表面上并接地的接地层; 其中通过将绝缘气体通过中心导体和绝缘管之间的间隙对流而辐射从中心导体产生的热量。
    • 5. 发明授权
    • Semiconductor integrated circuit and method for testing the same
    • 半导体集成电路及其测试方法
    • US06631486B1
    • 2003-10-07
    • US09405015
    • 1999-09-27
    • Yoshihide KomatsuTadahiro YoshidaYukio Arima
    • Yoshihide KomatsuTadahiro YoshidaYukio Arima
    • G01R3128
    • G01R31/31905G01R31/31926
    • A test enable signal Data_En is output from a data generator 11 in a tester 10 to a device under a test (DUT) 20. In the DUT 20, a first logic circuit 21 converts a signal pattern with an ordinary transfer rate, which has been stored on a register 28, into a high-transfer-rate signal pattern SpeedData_Tx with a high rate. And a transmitter 22 transmits the high-transfer-rate signal. During a test, the high-transfer-rate signal transmitted is received by, a receiver 23 with a switch 24 turned ON. Then, the high-transfer-rate signal received is output to a second logic circuit 26, which converts the high-transfer-rate signal into a low-transfer-rate signal Data_Rx with an ordinary rate. Finally, the low-transfer-rate signal is output to the tester 10 and compared to an expected value thereof by a comparator 12. In this manner, a semiconductor device operating at a high speed can be tested using a tester operating at a lower speed.
    • 测试使能信号Data_En从测试器10中的数据发生器11输出到被测设备(DUT)20。在DUT 20中,第一逻辑电路21以一般传输速率转换信号模式 存储在寄存器28中,以高速率转换成高传输速率信号模式SpeedData_Tx。 并且发射机22发送高传输速率信号。 在测试期间,传输的高传输速率信号由开关24接通的接收机23接收。 然后,所接收的高传输速率信号被输出到第二逻辑电路26,第二逻辑电路26将高传输速率信号以普通速率转换成低传输速率信号Data_Rx。 最后,将低传输速率信号输出到测试器10,并通过比较器12与其期望值进行比较。以这种方式,可以使用以较低速度操作的测试仪来测试以高速工作的半导体器件 。
    • 9. 发明授权
    • Binary digital data signal reproducing circuit in digital data
transmission system
    • 数字数据传输系统中的二进制数字数据信号再现电路
    • US4598412A
    • 1986-07-01
    • US700082
    • 1985-02-11
    • Tadahiro Yoshida
    • Tadahiro Yoshida
    • H04L25/03H04L25/24H04L25/08
    • H04L25/242
    • A reproducer for reproducing a binary digital data signal from a signal received at a receiver side. A pulse train is detected from the received signal at a pulse detector. Each pulse in the pulse train sets a first D-type flip-flop, which is, in turn, cleared by a clear pulse produced by a second D-type flip-flop in response to a clock pulse just after the first D-type flip-flop is set. The output of the first D-type flip-flop is applied to a data input terminal of a third D-type flip-flop and is taken into the third D-type flip-flop by the same clock pulse. The clock pulse repetition frequency is synchronous with the binary digital data signal. Thus, the reproduced binary digital data signal is obtained on an output of the third D-type flip-flop.
    • 一种用于从在接收机侧接收的信号再现二进制数字数据信号的再现器。 在脉冲检测器处从接收到的信号检测脉冲串。 脉冲串中的每个脉冲设置第一D型触发器,该第一D型触发器又由第二D型触发器产生的清除脉冲清除,以响应刚刚在第一D型触发器之后的时钟脉冲 触发器设置。 第一D型触发器的输出被施加到第三D型触发器的数据输入端,并被相同的时钟脉冲带入第三D型触发器。 时钟脉冲重复频率与二进制数字数据信号同步。 因此,在第三D型触发器的输出上获得再现的二进制数字数据信号。
    • 10. 发明授权
    • Clock synchronization device in data transmission system
    • 数据传输系统中的时钟同步装置
    • US4573173A
    • 1986-02-25
    • US618410
    • 1984-06-06
    • Tadahiro Yoshida
    • Tadahiro Yoshida
    • H04L7/02H04L7/033H04L7/00
    • H04L7/0338
    • A circuit for obtaining a clock pulse synchronized to a data signal received at a receiving side, which has a plurality of clock pulses having a repetition frequency equal to that of a clock in a transmission side but being different from one another in phase. On reception of the first data bit of the received data signal, the timing of the first data bit is detected at a detection circuit in reference to the plurality of clock pulses. According to the detected timing, a selector circuit selects one of the plurality of clock pulses with a predetermined constant phase difference from the received data signal.The detection circuit comprises D-type flip-flops, and the selector circuit comprises AND gates.
    • 一种用于获得与在接收侧接收的数据信号同步的时钟脉冲的电路,其具有多个时钟脉冲,所述时钟脉冲的重复频率等于发送侧的时钟的重复频率,但是彼此相位不同。 在接收到接收到的数据信号的第一数据位时,参考多个时钟脉冲在检测电路处检测第一数据位的定时。 根据检测到的定时,选择器电路从接收的数据信号中选择具有预定的恒定相位差的多个时钟脉冲之一。 检测电路包括D型触发器,选择电路包括与门。