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1. 发明授权

US5787464A Computer system including a dual memory configuration which supports on-line memory extraction and insertion 失效
标题翻译：计算机系统包括支持在线存储器提取和插入的双存储器配置
公开(公告)号：US5787464A
公开(公告)日：1998-07-28
申请号：US794604
申请日：1997-02-03
申请人： Ryokichi Yoshizawa , Takeshi Miyao , Shigenori Kaneko , Tomoaki Nakamura , Hidebumi Miyata
发明人： Ryokichi Yoshizawa , Takeshi Miyao , Shigenori Kaneko , Tomoaki Nakamura , Hidebumi Miyata
IPC分类号： G06F11/16 , G06F12/00 , G06F12/16 , G06F13/40 , G06F13/00 , G06F12/06
CPC分类号： G06F13/4081
摘要： A computer system and method for enabling memory expansion without shutting off the computer system are disclosed. The computer system has a dual memory configuration and supports memory insertion and extraction while being on-line. The memory content of one system may be copied to the memory of another system according to a predetermined priority or after a predetermined delay. Memory may be used efficiently during the insertion or extraction by securing a status management table expansion area in an expanded portion of memory. Memory may be expanded in computer systems that do not have an open memory slot by replacing the installed memory with a memory having a larger capacity.
摘要翻译：公开了一种用于在不关闭计算机系统的情况下实现存储器扩展的计算机系统和方法。计算机系统具有双存储器配置，并且在线时支持存储器插入和提取。一个系统的存储器内容可以根据预定的优先级或在预定的延迟之后复制到另一个系统的存储器。在插入或提取期间，可以通过将状态管理表扩展区域固定在存储器的扩展部分中来有效地使用存储器。通过用具有较大容量的存储器替换已安装的存储器，可以在没有打开内存插槽的计算机系统中扩展内存。

2. 发明授权

US06892261B2 Multiple operating system control method 失效
标题翻译：多操作系统控制方式
公开(公告)号：US06892261B2
公开(公告)日：2005-05-10
申请号：US10774486
申请日：2004-02-10
申请人： Hiroshi Ohno , Tomoaki Nakamura , Shigenori Kaneko , Ryokichi Yoshizawa , Naoshi Kato , Manabu Yamauchi , Toshiaki Arai , Tomoki Sekiguchi
发明人： Hiroshi Ohno , Tomoaki Nakamura , Shigenori Kaneko , Ryokichi Yoshizawa , Naoshi Kato , Manabu Yamauchi , Toshiaki Arai , Tomoki Sekiguchi
IPC分类号： G06F9/455 , G06F9/48 , G06F13/24
CPC分类号： G06F9/4812 , G06F9/45533 , G06F9/4843
摘要： An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.
摘要翻译：安装用于在单个CPU上执行的用于切换操作系统的操作系统间控制软件，并且交替地执行多个操作系统。控制程序仅在一个操作系统上执行，该控制程序控制受控设备。在另一个OS上执行监视控制程序和开发环境程序，并且对存储器空间进行分割，从而对控制程序的操作没有影响。可以使用单个CPU架构来建立更高的实时性能和可靠性。

3. 发明授权

US06715016B1 Multiple operating system control method 失效
公开(公告)号：US06715016B1
公开(公告)日：2004-03-30
申请号：US09585120
申请日：2000-06-01
申请人： Hiroshi Ohno , Tomoaki Nakamura , Shigenori Kaneko , Ryokichi Yoshizawa , Naoshi Kato , Manabu Yamauchi , Toshiaki Arai , Tomoki Sekiguchi
发明人： Hiroshi Ohno , Tomoaki Nakamura , Shigenori Kaneko , Ryokichi Yoshizawa , Naoshi Kato , Manabu Yamauchi , Toshiaki Arai , Tomoki Sekiguchi
IPC分类号： G06F1324
CPC分类号： G06F9/4812 , G06F9/45533 , G06F9/4843
摘要： An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.

4. 发明授权

US5579508A Main memory managing method and apparatus in which main memory is partitioned into three distinct areas 失效
标题翻译：主存储器管理方法和装置，其中主存储器被分成三个不同的区域
公开(公告)号：US5579508A
公开(公告)日：1996-11-26
申请号：US293334
申请日：1994-08-24
申请人： Ryokichi Yoshizawa , Tomoaki Nakamura , Shigenori Kaneko
发明人： Ryokichi Yoshizawa , Tomoaki Nakamura , Shigenori Kaneko
IPC分类号： G06F12/12 , G06F9/445 , G06F12/02 , G06F12/08
CPC分类号： G06F12/023
摘要： A main memory managing arrangement involves allotting a request program to one of three distinct areas of main memory by looking in an area managing table which stores head addresses and the capacities of the respective areas. The areas allocated in main memory correspond to a single OS area, a single first class program area and a single second class program area. An empty page managing table is also provided for indicating the presence or absence of an empty area conformable to a request in an allocated area. A request program is allocated to the allocated area when the presence of the empty area of required capacity is determined. The memory capacity for a resident program can be assured independently of the memory capacities for other programs to enhance reliability conformable to real-time process computers.
摘要翻译：主存储器管理装置包括通过查找存储头部地址的区域管理表和各个区域的容量来将请求程序分配给主存储器的三个不同区域中的一个。分配在主存储器中的区域对应于单个OS区域，单个第一类程序区域和单个第二类程序区域。还提供了一个空页面管理表，用于指示是否存在符合分配区域中的请求的空白区域。当确定所需容量的空区域的存在时，向所分配的区域分配请求程序。可以独立于其他程序的存储容量来确保驻留程序的存储容量，以增强与实时处理计算机兼容的可靠性。

5. 发明授权

US06216236B1 Processing unit for a computer and a computer system incorporating such a processing unit 失效
标题翻译：用于计算机的处理单元和包含这种处理单元的计算机系统
公开(公告)号：US06216236B1
公开(公告)日：2001-04-10
申请号：US09188903
申请日：1998-11-10
申请人： Takeshi Miyao , Manabu Araoka , Tomoaki Nakamura , Masayuki Tanji , Shigenori Kaneko , Koji Masui , Saburou Iijima , Nobuyasu Kanekawa , Shinichiro Kanekawa , Yoshiki Kobayashi , Hiroaki Fukumaru , Katsunori Tagiri
发明人： Takeshi Miyao , Manabu Araoka , Tomoaki Nakamura , Masayuki Tanji , Shigenori Kaneko , Koji Masui , Saburou Iijima , Nobuyasu Kanekawa , Shinichiro Kanekawa , Yoshiki Kobayashi , Hiroaki Fukumaru , Katsunori Tagiri
IPC分类号： G06F1134
CPC分类号： G06F11/187 , G06F11/1064 , G06F11/141 , G06F11/1604 , G06F11/1641 , G06F11/1666 , G06F11/1679 , G06F11/18 , G06F11/181 , G06F11/184 , G06F11/185 , G06F11/20 , G06F11/2007 , G06F11/2028 , G06F11/203 , G06F11/2035 , G06F11/2043 , G06F12/0833 , G11C29/74
摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020-1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.
摘要翻译：计算机系统具有经由一个或多个系统总线（1-1,1-2）连接的多个处理单元（2-1,2-2,2-n）。每个处理单元（2-1,2-2,2-n）在公共支撑板（PL）上具有三个或更多个处理器（20-1,20-2,20-3），并由公共时钟单元 1000）。三个处理器（20-1,20-2,20-3）执行相同的操作，并且通过比较三个处理器（20-1,20-2,20-3）的操作来检测处理器（20-1,20-2,20-3）中的故障（20-1,20-2,20-3）。如果一个处理器（20-1,20-2,20-3）失败，则可以在处理单元的其他两个处理器（20-1,20-2,20-3）中继续操作（2-1,2 -2,2-n），至少暂时在更换整个处理单元（2-1,2-2,2-n）之前。此外，处理单元（2-1,2-2,2-n）可以在时钟单元（1000）内具有多个时钟（A，B），具有切换装置，使得处理器（20-1， 20-2,20-n）通常从主时钟（A）接收时钟脉冲，但是如果主时钟（A）发生故障，则从辅助时钟（B）接收脉冲。在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。另外，多个高速缓冲存储器（220,221）可以共同地连接到处理器（20-1,20-2,20-3），使得一个高速缓冲存储器（220,221）的故障允许处理单元（2-1 ，2

6. 发明授权

US5901281A Processing unit for a computer and a computer system incorporating such a processing unit 失效
标题翻译：用于计算机的处理单元和包含这种处理单元的计算机系统
公开(公告)号：US5901281A
公开(公告)日：1999-05-04
申请号：US434288
申请日：1995-05-03
申请人： Takeshi Miyao , Manabu Araoka , Tomoaki Nakamura , Masayuki Tanji , Shigenori Kaneko , Koji Masui , Saburou Iijima , Nobuyasu Kanekawa , Shinichiro Kanekawa , Yoshiki Kobayashi , Hiroaki Fukumaru , Katsunori Tagiri
发明人： Takeshi Miyao , Manabu Araoka , Tomoaki Nakamura , Masayuki Tanji , Shigenori Kaneko , Koji Masui , Saburou Iijima , Nobuyasu Kanekawa , Shinichiro Kanekawa , Yoshiki Kobayashi , Hiroaki Fukumaru , Katsunori Tagiri
IPC分类号： G06F11/00 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G11C29/00 , G06F11/34
CPC分类号： G06F11/187 , G06F11/1064 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/1679 , G06F11/181 , G06F11/184 , G06F11/2007 , G06F11/2028 , G06F11/203 , G06F11/2035 , G06F11/2043 , G06F12/0833 , G06F11/1641 , G06F11/18 , G06F11/185 , G06F11/20 , G11C29/74
摘要： A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories may be connected in common to the processors, so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.
摘要翻译：计算机系统具有经由一个或多个系统总线连接的多个处理单元。每个处理单元在公共支撑板（PL）上具有三个或更多个处理器，并由公共时钟单元控制。三个处理器执行相同的操作，并且通过比较三个处理器的操作来检测处理器中的故障。如果一个处理器发生故障，则在更换整个处理单元之前，至少暂时在处理单元的其他两个处理器中继续操作。此外，处理单元可以在时钟单元内具有多个时钟（A，B），具有切换装置，使得处理器通常从主时钟（A）接收时钟脉冲，但是从辅助时钟（B ）如果主时钟（A）失败。在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。此外，多个高速缓冲存储器可以共同地连接到处理器，使得一个高速缓冲存储器的故障允许处理单元使用另一高速缓冲存储器继续操作。可以通过直接比较来实现高速缓冲存储器的内容的一致性，并且还可以使用比较方法来使处理器的内部高速缓冲存储器中的数据与外部高速缓冲存储器中的数据不同。协议的一致性还可以确保不同处理器单元的高速缓存中的数据总是正确的。

7. 发明授权

US06711605B2 Multi OS configuration method and computer system 失效
公开(公告)号：US06711605B2
公开(公告)日：2004-03-23
申请号：US09836471
申请日：2001-04-18
申请人： Tomoki Sekiguchi , Toshiaki Arai , Shigenori Kaneko , Hiroshi Ohno , Taro Inoue , Takashi Shibata
发明人： Tomoki Sekiguchi , Toshiaki Arai , Shigenori Kaneko , Hiroshi Ohno , Taro Inoue , Takashi Shibata
IPC分类号： G06F1700
CPC分类号： G06F9/4843 , G06F9/45537 , G06F11/261
摘要： A computer system of a multi-operation-system (multi-OS) has a main memory having a memory area for a first OS and a memory area for a second OS, both the areas being independent from each other, and a plurality of I/O devices divisionally allocated to the first OS and the second OS. The first OS is loaded in the first OS memory area, and thereafter when the first OS is operated, the second OS is loaded in the second OS memory area and initialized. When the first OS is operated, the first OS hardware resources and the second OS hardware resources are registered by the first OS. Thereafter when the first OS is operated, the first OS inhibits the registration of an interrupt number already allocated to the second OS I/O device. In response to an interrupt request from a second OS I/O device, the second OS starts operating.

8. 发明授权

US6138248A Common disk unit multi-computer system 失效
标题翻译：普通磁盘机多计算机系统
公开(公告)号：US6138248A
公开(公告)日：2000-10-24
申请号：US1224
申请日：1997-12-30
申请人： Masahiko Saito , Hidehito Takewa , Kenichi Kurosawa , Yoshihiro Miyazaki , Shigenori Kaneko
发明人： Masahiko Saito , Hidehito Takewa , Kenichi Kurosawa , Yoshihiro Miyazaki , Shigenori Kaneko
IPC分类号： G06F11/20 , G06F11/16 , G06F12/08 , G06F15/16 , G06F15/177
CPC分类号： G06F11/20 , G06F11/0727 , G06F11/2028 , G06F11/2046 , G06F11/0793 , G06F11/2038
摘要： A computer and a backup computer exchange periodic report signal transmissions by way of SVP115. When there is no periodic report signal transmission from the main computer, the backup computer makes a main computer status inquiry and if one location is malfunctioning resets the main computer by way of the SVP115 and continues the processing. When permanent damage is present, the SVP115 continually resets the main computer and controls MOS switches of the common disk unit to isolate the SCSI from the main computer and continue the main computer processing.
摘要翻译：计算机和备份计算机通过SVP115交换周期性报告信号传输。当主计算机没有定期报告信号传输时，备份计算机进行主计算机状态查询，如果一个位置发生故障，则通过SVP115复位主机，并继续处理。当存在永久性损坏时，SVP115会连续复位主计算机，并控制公共磁盘单元的MOS开关，使SCSI与主计算机隔离，并继续进行主机处理。

9. 发明授权

US06772419B1 Multi OS configuration system having an interrupt process program executes independently of operation of the multi OS 失效
标题翻译：具有中断处理程序的多OS配置系统独立于多OS的操作而执行
公开(公告)号：US06772419B1
公开(公告)日：2004-08-03
申请号：US09151270
申请日：1998-09-11
申请人： Tomoki Sekiguchi , Toshiaki Arai , Shigenori Kaneko , Hiroshi Ohno , Taro Inoue , Takashi Shibata
发明人： Tomoki Sekiguchi , Toshiaki Arai , Shigenori Kaneko , Hiroshi Ohno , Taro Inoue , Takashi Shibata
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/45537 , G06F11/261
摘要： A computer system of a multi-operation-system (multi-OS) has a main memory having a memory area for a first OS and a memory area for a second OS, both the areas being independent from each other, and a plurality of I/O devices divisionally allocated to the first OS and the second OS. The first OS is loaded in the first OS memory area, and thereafter when the first OS is operated, the second OS is loaded in the second OS memory area and initialized. When the first OS is operated, the first OS hardware resources and the second OS hardware resources are registered by the first OS. Thereafter when the first OS is operated, the first OS inhibits the registration of an interrupt number already allocated to the second OS I/O device. In response to an interrupt request from a second OS I/O device, the second OS starts operating.
摘要翻译：多操作系统（multi-OS）的计算机系统具有主存储器，其具有用于第一OS的存储区域和用于第二OS的存储区域，两个区域彼此独立，并且多个I / O设备分配到第一个操作系统和第二个操作系统。第一OS被加载在第一OS存储器区域中，之后当第一OS被操作时，第二OS被加载到第二OS存储器区域并被初始化。当操作第一操作系统时，由第一操作系统登记第一操作系统硬件资源和第二操作系统硬件资源。此后，当第一OS被操作时，第一OS禁止已经分配给第二OS I / O设备的中断号码的注册。响应于来自第二OS I / O设备的中断请求，第二个OS开始运行。

10. 发明授权

US07712104B2 Multi OS configuration method and computer system 失效
标题翻译：多操作系统配置方法和计算机系统
公开(公告)号：US07712104B2
公开(公告)日：2010-05-04
申请号：US10878185
申请日：2004-06-29
申请人： Tomoki Sekiguchi , Toshiaki Arai , Shigenori Kaneko , Hiroshi Ohno , Taro Inoue , Takashi Shibata
发明人： Tomoki Sekiguchi , Toshiaki Arai , Shigenori Kaneko , Hiroshi Ohno , Taro Inoue , Takashi Shibata
IPC分类号： G06F9/46 , G06F9/455
CPC分类号： G06F9/4843 , G06F9/45537 , G06F11/261
摘要： A computer system of a multi-operation-system (multi-OS) has a main memory having a memory area for a first OS and a memory area for a second OS, both the areas being independent from each other, and a plurality of I/O devices divisionally allocated to the first OS and the second OS. The first OS is loaded in the first OS memory area, and thereafter when the first OS is operated, the second OS is loaded in the second OS memory area and initialized. When the first OS is operated, the first OS hardware resources and the second OS hardware resources are registered by the first OS. Thereafter when the first OS is operated, the first OS inhibits the registration of an interrupt number already allocated to the second OS I/O device. In response to an interrupt request from a second OS I/O device, the second OS starts operating.
摘要翻译：多操作系统（multi-OS）的计算机系统具有主存储器，其具有用于第一OS的存储区域和用于第二OS的存储区域，两个区域彼此独立，并且多个I / O设备分配到第一个操作系统和第二个操作系统。第一OS被加载在第一OS存储器区域中，之后当第一OS被操作时，第二OS被加载到第二OS存储器区域并被初始化。当操作第一操作系统时，由第一操作系统登记第一操作系统硬件资源和第二操作系统硬件资源。此后，当第一OS被操作时，第一OS禁止已经分配给第二OS I / O设备的中断号码的注册。响应于来自第二OS I / O设备的中断请求，第二个OS开始运行。

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