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1. 发明授权

US5436559A Method for testing semiconductor device 失效
标题翻译：半导体器件测试方法
公开(公告)号：US5436559A
公开(公告)日：1995-07-25
申请号：US109957
申请日：1993-08-23
申请人： Ryoichi Takagi , Tetsuo Tada , Koji Tanaka
发明人： Ryoichi Takagi , Tetsuo Tada , Koji Tanaka
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3193
CPC分类号： G01R31/2844 , G01R31/31924 , G01R31/31937
摘要： A method of testing a semiconductor device operating according to predetermined testing information. An output signal of the semiconductor device is received through a signal transmission line and a reference voltage is generated in accordance with an expected logical level of the output signal. The reference voltage is compared with a voltage of the output signal thus received and a current flow is supplied to the signal transmission line in accordance with the result. A logical level of the output signal thus received is determined and a decision is made whether the semiconductor device operates correctly.
摘要翻译：一种测试根据预定测试信息操作的半导体器件的方法。通过信号传输线接收半导体器件的输出信号，并根据输出信号的预期逻辑电平产生参考电压。将参考电压与如此接收的输出信号的电压进行比较，并根据结果将电流提供给信号传输线。确定如此接收的输出信号的逻辑电平，并且确定半导体器件是否正常工作。

2. 发明授权

US5266894A Apparatus and method for testing semiconductor device 失效
标题翻译：半导体器件测试装置及方法
公开(公告)号：US5266894A
公开(公告)日：1993-11-30
申请号：US805140
申请日：1991-12-11
申请人： Ryoichi Takagi , Tetsuo Tada , Koji Tanaka
发明人： Ryoichi Takagi , Tetsuo Tada , Koji Tanaka
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3193
CPC分类号： G01R31/2844 , G01R31/31924 , G01R31/31937
摘要： A semiconductor testing apparatus includes a comparator for receiving a signal output to a pin terminal of a semiconductor device under test through a transmission line and determining a logical level of the received signal. Semiconductor testing apparatus 1 further includes a current supply circuit for comparing a voltage of an input terminal of comparator with a reference voltage applied by reference voltage sources and supplying a current to transmission line. When a signal ringing on transmission line and a reflection with undershoot and overshoot at input terminal occur, current supply circuit supplies a current to transmission line in accordance with a relationship of magnitude between the voltage at input terminal and the reference voltage. The current supply to transmission line is made to inhibit the overshoot and undershoot of the signal. This allows comparator to carry out a functional testing and a measurement of DC/AC characteristics of a semiconductor device at precise timing and at high speed.
摘要翻译：半导体测试装置包括：比较器，用于通过传输线接收输出到被测半导体器件的引脚端子的信号，并确定接收信号的逻辑电平。半导体测试装置1还包括电流供应电路，用于将比较器的输入端的电压与由参考电压源施加的参考电压进行比较，并将电流提供给传输线。当传输线上的信号振铃和在输入端子处产生下冲和过冲的反射出现时，电流源电路根据输入端电压和参考电压之间的大小关系向传输线提供电流。传输线的电流供应是为了抑制信号的过冲和下冲。这允许比较器在精确的定时和高速下进行半导体器件的DC / AC特性的功能测试和测量。

3. 发明授权

US4961052A Probing plate for wafer testing 失效
标题翻译：探测板用于晶圆测试
公开(公告)号：US4961052A
公开(公告)日：1990-10-02
申请号：US380427
申请日：1989-07-17
申请人： Tetsuo Tada , Ryoichi Takagi , Masanobu Kohara
发明人： Tetsuo Tada , Ryoichi Takagi , Masanobu Kohara
IPC分类号： G01R31/26 , G01R1/073 , H01L21/66
CPC分类号： G01R1/07342
摘要： A probing plate for wafer testing is provided with a plurality of probes arranged so as to correspond to a plurality of bonding pads of semiconductor devices fabricated on a semiconductor wafer. The probing plate has a base plate formed of an insulating material, such as a photosensitive glass, and has contact fingers each having a raised portion in the free end thereof, contact conductors respectively formed on the surfaces of the raised portions of the contact fingers so as to be brought into contact with the corresponding bonding pads, and wiring conductors formed in a predetermined pattern on the surface of the base plate so as to extend respectively from the contact conductors. The contact conductors and the wiring conductors are formed simultaneously by a photolithographic process. The contact fingers and the raised portions thereof are also formed by subjecting the base plate to a photolithographic process. Forming the contact conductors over the surfaces of the raised portions of the contact fingers prevents accidental contact of the contact conductors with the bonding pads of semiconductor devices other than the objective semiconductor devices.
摘要翻译：用于晶片测试的探测板设置有多个探针，其布置成对应于制造在半导体晶片上的多个半导体器件的焊盘。探测板具有由诸如感光玻璃的绝缘材料形成的基板，并且具有在其自由端中具有凸起部分的接触指状物，分别形成在接触指尖的凸起部分的表面上的接触导体与相应的接合焊盘和在基板的表面上以预定图案形成的布线导体接触，以便分别从接触导体延伸。接触导体和布线导体通过光刻工艺同时形成。接触指及其凸起部分也通过使基板进行光刻工艺而形成。在接触指状物的凸起部分的表面上形成接触导体可防止接触导体与物镜半导体器件以外的半导体器件的接合焊盘意外接触。

4. 发明授权

US07080302B2 Semiconductor device and test system therefor 失效
公开(公告)号：US07080302B2
公开(公告)日：2006-07-18
申请号：US10163579
申请日：2002-06-07
申请人： Ryoichi Takagi
发明人： Ryoichi Takagi
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/318566 , G01R31/318572
摘要： The present invention provides a test system for a semiconductor device, the test system comprising: a test data generator for generating test data, the test data generator being provided in an output section; a delay circuit for, in order to use as expected-value data the test data after the test data is transferred through inside a chip, adjusting a time difference between the test data and the expected-value data; a comparator for, against the expected-value data, comparing and verifying the test data after the test data is transferred outside the chip, the comparator being provided in an input section; and an external wiring for connecting an output pin connected to the test data generator and an input pin connected to the comparator.

5. 发明授权

US06356096B2 Test board for testing a semiconductor device utilizing first and second delay elements in a signal-transmission-path 失效
标题翻译：用于测试在信号传输路径中利用第一和第二延迟元件的半导体器件的测试板
公开(公告)号：US06356096B2
公开(公告)日：2002-03-12
申请号：US09146173
申请日：1998-09-03
申请人： Ryoichi Takagi , Masahiro Ueda , Yoshinori Deguchi
发明人： Ryoichi Takagi , Masahiro Ueda , Yoshinori Deguchi
IPC分类号： G01R3126
CPC分类号： G01R31/31937
摘要： A test board for testing a semiconductor device. The semiconductor device includes at least first and second input terminals and an input/output buffer cell for buffering a signal obtained from the first input terminal to output an internal signal. The operation of the semiconductor device is controlled by a signal obtained from the second input terminal. The test board includes a first delay element for delaying a signal to be transmitted therethrough for a first signal propagation delay time and a second delay element for delaying a signal to be transmitted therethrough for a second signal propagation delay time different from the first signal propagation delay time. A signal-transmission-path receives a first test signal and forms, a first signal transmission path along which the first test signal is transmitted through the first delay element to the first input terminal of the semiconductor device, and a second transmission path along which the first test signal is transmitted through the second delay element to the second input terminal of the semiconductor device.
摘要翻译：用于测试半导体器件的测试板。半导体器件至少包括第一和第二输入端子以及用于缓冲从第一输入端子获得的信号以输出内部信号的输入/输出缓冲单元。半导体器件的操作由从第二输入端获得的信号控制。测试板包括第一延迟元件，用于延迟第一信号传播延迟时间中通过其传输的信号，以及第二延迟元件，用于延迟要通过其传输的信号用于与第一信号传播延迟不同的第二信号传播延迟时间时间。信号传输路径接收第一测试信号并形成第一信号传输路径，第一测试信号沿着第一信号传输路径通过第一延迟元件传输到半导体器件的第一输入端;以及第二传输路径，第一测试信号通过第二延迟元件发送到半导体器件的第二输入端。

6. 发明授权

US5844263A Semiconductor integrated device having independent circuit blocks and a power breaking means for selectively supplying power to the circuit blocks 失效
标题翻译：具有独立电路块的半导体集成器件和用于向电路块选择性供电的断电装置
公开(公告)号：US5844263A
公开(公告)日：1998-12-01
申请号：US837940
申请日：1997-04-28
申请人： Mikio Asai , Masahiko Hyozo , Ryoichi Takagi
发明人： Mikio Asai , Masahiko Hyozo , Ryoichi Takagi
IPC分类号： H01L27/04 , H01L21/822 , H01L27/088 , H01L27/10
CPC分类号： H01L27/088
摘要： A semiconductor integrated device including a first circuit block, a second circuit block, a first supply interconnection connected to the first circuit block to supply power thereto, a second supply interconnection connecting the first supply interconnection to the second circuit block, and a switch inserted across the first and second supply interconnections. The switch has a structure equivalent to a plurality of switching elements disposed in parallel on a substrate. The switch is opened by a break command output from the first circuit block so that the second supply interconnection is disconnected from the first supply interconnection, thereby preventing a standby current from flowing to the second circuit block when it is unused. This can solve a problem of a conventional semiconductor integrated device in that the standby current flowing to the second circuit block wastes power even if the second block is not used.
摘要翻译：一种半导体集成装置，包括第一电路块，第二电路块，连接到第一电路块以向其供电的第一电源互连，将第一电源互连连接到第二电路块的第二电源互连以及跨第第一和第二供电互连。开关具有与在基板上平行设置的多个开关元件相当的结构。通过从第一电路块输出的断开命令来打开开关，使得第二电源互连与第一电源互连断开，从而当不使用时防止待机电流流向第二电路块。这可以解决传统的半导体集成器件的问题在于，即使不使用第二块，流向第二电路块的待机电流也会浪费电力。

7. 发明授权

US6150831A Test method and device for semiconductor circuit 失效
标题翻译：半导体电路的测试方法和器件
公开(公告)号：US6150831A
公开(公告)日：2000-11-21
申请号：US990800
申请日：1997-12-15
申请人： Mikio Asai , Ryoichi Takagi
发明人： Mikio Asai , Ryoichi Takagi
IPC分类号： G01R27/02 , G01R31/28
CPC分类号： G01R31/2884
摘要： A semiconductor test device capable of solving a problem of a conventional one in that in the resistance measurement of a semiconductor integrated circuit it was difficult for the measurement error due to contact resistance or wiring resistance to be limited within a desired amount. The present semiconductor test device includes, in a semiconductor integrated circuit having a first semiconductor switch functioning as a pullup resistor and a second semiconductor switch functioning as a pulldown resistor, a measuring circuit for bringing the first and second semiconductor switches into conduction at the same time in response to a signal fed from a control circuit, a voltage measuring circuit for measuring the voltage at a connecting point between the two semiconductor switches, and a current measuring circuit for measuring a through current flowing through the two semiconductor switches.
摘要翻译：能够解决现有技术问题的半导体测试装置，其中在半导体集成电路的电阻测量中，由于接触电阻或布线电阻而导致的测量误差难以限制在期望的量内。本半导体测试装置包括在具有用作上拉电阻的第一半导体开关和用作下拉电阻的第二半导体开关的半导体集成电路中，用于同时使第一和第二半导体开关导通的测量电路响应于从控制电路馈送的信号，用于测量两个半导体开关之间的连接点处的电压的电压测量电路和用于测量流过两个半导体开关的贯通电流的电流测量电路。

8. 发明授权

US06704897B1 Semiconductor device and the test system for the same 有权
标题翻译：半导体器件和测试系统相同
公开(公告)号：US06704897B1
公开(公告)日：2004-03-09
申请号：US09669577
申请日：2000-09-26
申请人： Ryoichi Takagi
发明人： Ryoichi Takagi
IPC分类号： G01R3128
CPC分类号： G01R31/31937 , G01R31/31715 , G01R31/31905 , G01R31/3191
摘要： A test system includes a semiconductor device having a circuit configuration including an input buffer circuit, an output buffer circuit, and an internal logic, a random data generation circuit being provided at the front stage of the output buffer circuit; a random data generator, incorporating a random data generation circuit, for applying a random data to an input of the input buffer circuit from the random data generation circuit; and a test board on which the semiconductor device and random data generator is mounted and electrically connected to each other.
摘要翻译：测试系统包括具有包括输入缓冲电路，输出缓冲电路和内部逻辑的电路结构的半导体器件，随机数据产生电路设置在输出缓冲电路的前级; 随机数据生成器，包括随机数据生成电路，用于从随机数据生成电路将随机数据应用于输入缓冲器电路的输入; 以及半导体器件和随机数据发生器安装并彼此电连接的测试板。

9. 发明授权

US06486690B1 Device under test board and testing method 失效
标题翻译：设备测试板和测试方法
公开(公告)号：US06486690B1
公开(公告)日：2002-11-26
申请号：US09522014
申请日：2000-03-09
申请人： Ryoichi Takagi , Masahiko Hyozo
发明人： Ryoichi Takagi , Masahiko Hyozo
IPC分类号： G01R3102
CPC分类号： G01R1/07371
摘要： A device under test (DUT) board for testing is electrically connected to a solder ball of a package. A contactor of the board is directly attached to the solder ball. Thus, there is little influence by bouncing of a power source and ground, even when an LSI under test is operated at high speed and low voltage, and malfunctions are rare.
摘要翻译：用于测试的被测设备（DUT）板电连接到封装的焊球。板的接触器直接连接到焊球上。因此，即使被测试的LSI在高速低电压下工作，即使电源和接地的弹跳几乎没有影响，故障也很少。

10. 发明授权

US06282680B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06282680B1
公开(公告)日：2001-08-28
申请号：US09217593
申请日：1998-12-21
申请人： Ryoichi Takagi , Katsushi Asahina
发明人： Ryoichi Takagi , Katsushi Asahina
IPC分类号： G01R3128
CPC分类号： G01R31/3016
摘要： Provided is a semiconductor device having an I/O buffer cell capable of performing a timing verification test of high accuracy. A phase comparator (2) compares the phase of data (DATA) and that of a clock (CLK) and outputs a phase comparison result to a first input of an MUX (3). A test mode signal (STM1) inputted from a test mode terminal (14) is provided to the control input of the MUX (3) through a test mode input section (4). The MUX (3) receives at its second input the output signal of an internal logic (50) through a signal input section (9) and, based on the test mode signal (STM1), outputs either the phase comparison result or the output signal of the internal logic (50), to the input section of a driver (8).
摘要翻译：提供了具有能够执行高精度的定时验证测试的I / O缓冲单元的半导体器件。相位比较器（2）比较数据（DATA）与时钟（CLK）的相位，并将相位比较结果输出到MUX（3）的第一输入端。从测试模式端子（14）输入的测试模式信号（STM1）通过测试模式输入部分（4）提供给MUX（3）的控制输入端。 MUX（3）在其第二输入端通过信号输入部分（9）接收内部逻辑（50）的输出信号，并且基于测试模式信号（STM1），输出相位比较结果或输出信号的内部逻辑（50）发送到驱动器（8）的输入部分。

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