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1. 发明授权

US5844263A Semiconductor integrated device having independent circuit blocks and a power breaking means for selectively supplying power to the circuit blocks 失效
标题翻译：具有独立电路块的半导体集成器件和用于向电路块选择性供电的断电装置
公开(公告)号：US5844263A
公开(公告)日：1998-12-01
申请号：US837940
申请日：1997-04-28
申请人： Mikio Asai , Masahiko Hyozo , Ryoichi Takagi
发明人： Mikio Asai , Masahiko Hyozo , Ryoichi Takagi
IPC分类号： H01L27/04 , H01L21/822 , H01L27/088 , H01L27/10
CPC分类号： H01L27/088
摘要： A semiconductor integrated device including a first circuit block, a second circuit block, a first supply interconnection connected to the first circuit block to supply power thereto, a second supply interconnection connecting the first supply interconnection to the second circuit block, and a switch inserted across the first and second supply interconnections. The switch has a structure equivalent to a plurality of switching elements disposed in parallel on a substrate. The switch is opened by a break command output from the first circuit block so that the second supply interconnection is disconnected from the first supply interconnection, thereby preventing a standby current from flowing to the second circuit block when it is unused. This can solve a problem of a conventional semiconductor integrated device in that the standby current flowing to the second circuit block wastes power even if the second block is not used.
摘要翻译：一种半导体集成装置，包括第一电路块，第二电路块，连接到第一电路块以向其供电的第一电源互连，将第一电源互连连接到第二电路块的第二电源互连以及跨第第一和第二供电互连。开关具有与在基板上平行设置的多个开关元件相当的结构。通过从第一电路块输出的断开命令来打开开关，使得第二电源互连与第一电源互连断开，从而当不使用时防止待机电流流向第二电路块。这可以解决传统的半导体集成器件的问题在于，即使不使用第二块，流向第二电路块的待机电流也会浪费电力。

2. 发明授权

US5894172A Semiconductor device with identification function 失效
标题翻译：半导体器件具有识别功能
公开(公告)号：US5894172A
公开(公告)日：1999-04-13
申请号：US745273
申请日：1996-11-08
申请人： Masahiko Hyozo , Toshiyuki Tsujii , Tetsuo Tada , Hiroshi Noda , Ryouichi Takagi , Mikio Asai
发明人： Masahiko Hyozo , Toshiyuki Tsujii , Tetsuo Tada , Hiroshi Noda , Ryouichi Takagi , Mikio Asai
IPC分类号： H01L21/02 , G05B19/12 , G06K7/06 , G06K19/06 , G06K19/067 , H01L23/544 , H01L29/06 , H01L31/0203 , H01L23/04
CPC分类号： H01L23/544 , G05B19/128 , G06K19/06018 , G06K19/06037 , G06K19/067 , G06K7/065 , G05B2219/25294 , G06K2019/06271 , H01L2223/54406 , H01L2223/5442 , H01L2223/5444 , H01L2223/54473 , H01L2223/5448 , H01L2223/54486 , H01L29/0657 , H01L2924/0002
摘要： A bare chip (1) is rectangular, and has a front surface (1a) on the center of which semiconductor elements are integrated and a back surface. Notches (2) are formed on a side of the bare chip (1) according to the kind of the semiconductor elements integrated on the bare chip (1). The notches (2) are oblong and extend through the bare chip (1) from the front surface (1a) to the back surface. For example, assuming that the notch (2) represents "1" and a portion without the notch (2) represents "0", one-bit information is obtained according to the presence or absence of the notch (2). When detection of several portions is made, binary information according to a detection result, i.e., information regarding the type of the bare chip (1), is obtained. For detection of the presence or absence of the notch (2), the bare chip (1) is irradiated with light, and then whether the light goes through the notch (2) or is intercepted by the bare chip (1) is detected. Thus, a semiconductor device which allows easy identification of its type is provided.
摘要翻译：裸芯片（1）是矩形的，并且在其半导体元件集成的中心上具有前表面（1a）和后表面。根据集成在裸芯片（1）上的半导体元件的种类，在裸芯片（1）的一侧形成凹口（2）。凹口（2）是长圆形的，并且通过裸芯片（1）从前表面（1a）延伸到后表面。例如，假设凹口（2）表示“1”，没有凹口（2）的部分表示“0”，则根据凹口（2）的存在或不存在获得一位信息。当进行几个部分的检测时，获得根据检测结果的二进制信息，即关于裸芯片（1）的类型的信息。为了检测凹口（2）的存在或不存在，用光照射裸芯片（1），然后检测光是否穿过凹口（2）或被裸芯片（1）截取。因此，提供了容易识别其类型的半导体器件。

3. 发明授权

US06486690B1 Device under test board and testing method 失效
标题翻译：设备测试板和测试方法
公开(公告)号：US06486690B1
公开(公告)日：2002-11-26
申请号：US09522014
申请日：2000-03-09
申请人： Ryoichi Takagi , Masahiko Hyozo
发明人： Ryoichi Takagi , Masahiko Hyozo
IPC分类号： G01R3102
CPC分类号： G01R1/07371
摘要： A device under test (DUT) board for testing is electrically connected to a solder ball of a package. A contactor of the board is directly attached to the solder ball. Thus, there is little influence by bouncing of a power source and ground, even when an LSI under test is operated at high speed and low voltage, and malfunctions are rare.
摘要翻译：用于测试的被测设备（DUT）板电连接到封装的焊球。板的接触器直接连接到焊球上。因此，即使被测试的LSI在高速低电压下工作，即使电源和接地的弹跳几乎没有影响，故障也很少。

4. 发明授权

US06275055B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06275055B1
公开(公告)日：2001-08-14
申请号：US09286291
申请日：1999-04-06
申请人： Masahiko Hyozo , Katsushi Asahina
发明人： Masahiko Hyozo , Katsushi Asahina
IPC分类号： G01R3128
CPC分类号： G01R31/318558 , G01R31/3004 , G01R31/31715
摘要： A semiconductor integrated circuit, in which an input buffer, an output buffer, and an input/output buffer connected to signal pins respectively each as an object for a DC test are connected to a single DC test pin through discretely provided switches, all the switches are OFF in an ordinary state, and when the DC test is to be performed, the switches are successively turned ON one by one in a state where the DC test pin is connected to an LSI tester. With the operation, various types of DC test such as a pin contest, an input leak test and an output voltage test can be performed by using a LSI tester having a smaller number of pins than a number of pins in an LSI without requiring a connection such that the signal pins as objects for the test are in one-to-one correspondence with the pin electronics in the LSI tester.
摘要翻译：其中分别连接到信号引脚作为直流测试对象的输入缓冲器，输出缓冲器和输入/输出缓冲器的半导体集成电路通过离散地提供的开关连接到单个DC测试引脚，所有开关在通常状态下为OFF，当要进行直流测试时，在直流测试引脚连接到LSI测试仪的状态下，开关依次连续接通。通过该操作，可以通过使用具有比LSI中的引脚数少的引脚数的LSI测试器来进行诸如引脚比较，输入泄漏测试和输出电压测试的各种类型的直流测试，而不需要连接使得作为测试对象的信号引脚与LSI测试仪中的引脚电子器件一一对应。

5. 发明授权

US06519728B2 Semiconductor integrated circuit having test circuit 失效
标题翻译：具有测试电路的半导体集成电路
公开(公告)号：US06519728B2
公开(公告)日：2003-02-11
申请号：US09303624
申请日：1999-05-03
申请人： Toshiyuki Tsujii , Masahiko Hyozo
发明人： Toshiyuki Tsujii , Masahiko Hyozo
IPC分类号： G01R3128
CPC分类号： G01R31/318572 , G01R31/2884
摘要： A semiconductor integrated circuit has a test circuit in which signal pad (15) to input a switching signal TM is formed on a non-mounting surface of a LSI and one group of signal pads (11 to 13) formed on the non-mounting surface and signal pads (16 to 18) formed on a mounting surface is selected based on a signal level of the switching signal TM.
摘要翻译：半导体集成电路具有测试电路，其中输入切换信号TM的信号焊盘（15）形成在LSI的非安装表面上，并且形成在非安装表面上的一组信号焊盘（11至13）并且基于开关信号TM的信号电平来选择形成在安装表面上的信号焊盘（16至18）。

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