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1. 发明授权

US6002631A Semiconductor memory device having a mode in which a plurality of data are simultaneously read out of memory cells of one row and different columns 失效
标题翻译：具有从一行和不同列的存储单元中同时读出多个数据的模式的半导体存储器件
公开(公告)号：US6002631A
公开(公告)日：1999-12-14
申请号：US982534
申请日：1997-12-02
申请人： Ryo Haga , Tomoaki Yabe , Shinji Miyano
发明人： Ryo Haga , Tomoaki Yabe , Shinji Miyano
IPC分类号： G11C11/409 , G11C7/10 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C7/1018 , G11C7/1045 , G11C8/12
摘要： Even-numbered columns are arranged in the first memory cell array (bank), and odd-numbered columns are arranged in the second memory cell array (bank). A column address signal is input to an adder through a buffer. When data is read out of two or more columns, the adder generates a column address signal whose address value is more than that of the column address signal by one. The adder supplies a first column decoder with a column address signal for addressing an even-numbered column and supplies a second column decoder with a column address signal for addressing an odd-numbered column. Since the even-numbered columns and odd-numbered columns are arranged in their separate memory cell arrays, data read out of continuous two or more columns do not collide with each other.
摘要翻译：偶数列布置在第一存储单元阵列（bank）中，奇数列排列在第二存储单元阵列（bank）中。列地址信号通过缓冲器输入到加法器。当从两个或多个列读出数据时，加法器产生地址值大于列地址信号的列地址信号。加法器为第一列解码器提供列地址信号，用于寻址偶数列，并向第二列解码器提供用于寻址奇数列的列地址信号。由于偶数列和奇数列排列在其分开的存储单元阵列中，所以从连续的两个或更多个列读出的数据不会彼此冲突。

2. 发明授权

US06429521B1 Semiconductor integrated circuit device and its manufacturing method 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06429521B1
公开(公告)日：2002-08-06
申请号：US09531177
申请日：2000-03-21
申请人： Osamu Wada , Ryo Haga , Tomoaki Yabe , Shinji Miyano
发明人： Osamu Wada , Ryo Haga , Tomoaki Yabe , Shinji Miyano
IPC分类号： H01L2348
CPC分类号： H01L23/528 , H01L27/118 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).
摘要翻译：在半导体基板上，形成有由金属布线层（例如铝布线）形成的具有三层布线层的第一宏观单元和具有由金属布线形成的三层布线层的第二宏观单元层与第一个宏单元类似。第一宏单元形成为具有三个布线层的布线结构，尽管最初所需数量的金属布线层是两个。第一宏单元上的各层的金属布线层由与第二宏单元上的各层的金属布线层相同的材料形成。此外，各层的金属布线层形成为具有相同的膜厚度。为了将第一和第二宏单元彼此连接，形成宏布线布置在第三布线层（最上布线层）中。

3. 发明授权

US5754481A Clock synchronous type DRAM with latch 失效
标题翻译：时钟同步型DRAM带锁存器
公开(公告)号：US5754481A
公开(公告)日：1998-05-19
申请号：US857559
申请日：1997-05-16
申请人： Tomoaki Yabe , Kenji Numata , Katsuhiko Sato , Ryo Haga , Shinji Miyano , Tohru Furuyama
发明人： Tomoaki Yabe , Kenji Numata , Katsuhiko Sato , Ryo Haga , Shinji Miyano , Tohru Furuyama
IPC分类号： G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1072 , G11C7/1078
摘要： A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate. The write circuit writes data into the data latch in synchronism with a clock signal. At the time of writing data into the memory cells, data is previously supplied to the data latch by the write circuit and latched in the data latch, and after the transfer gate control circuit controls the transfer gate to supply data to the bit line pairs from the data latch, the sense amplifier control circuit activates the sense amplifier.
摘要翻译：半导体存储器件包括存储单元阵列，行解码器，位线对，读出放大器，读出放大器控制电路，数据锁存器，传输门，传输门控制电路和写电路。存储单元阵列具有以阵列形式排列的动态存储单元。行解码器解码行地址信号以选择存储单元阵列的所需行中的一行。每个位线对连接到布置在存储单元阵列的相应列上的存储单元的每一个。读出放大器放大在配对位线上读出的数据，并将数据反馈给配对的位线以保存数据。读出放大器控制电路控制读出放大器的工作。数据锁存器锁存读出数据和写入数据。传输门在数据锁存器和读出放大器之间传送数据。传输门控制电路控制传输门。写入电路与时钟信号同步地将数据写入数据锁存器。在将数据写入存储器单元时，数据预先由写入电路提供给数据锁存器并锁存在数据锁存器中，并且在传输门控制电路控制传输门以向位线对提供数据之后数据锁存器，读出放大器控制电路激活读出放大器。

4. 发明授权

US5555523A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5555523A
公开(公告)日：1996-09-10
申请号：US556148
申请日：1995-11-09
申请人： Ryo Haga , Tomoaki Yabe , Shinji Miyano , Kenji Numata
发明人： Ryo Haga , Tomoaki Yabe , Shinji Miyano , Kenji Numata
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4091 , G11C11/4094 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/4094
摘要： A semiconductor memory device comprises a plurality of memory cells including at least a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell and paired with the first bit line, an equalizer connected between the first and second bit lines, an amplifier connected between the first and second bit lines, a first driving signal line connected to the amplifier and drives the amplifier, a second driving signal line connected to the amplifier and paired with the first driving signal line, a driver for driving the amplifier and connected to the first and second driving signal lines and containing a precharger for presetting the potentials of the first and second driving signal lines to a predetermined precharge potential and a driving signal supply circuit for supplying a driving signal to the first and second driving signal lines, and a control circuit for controlling the equalizer and the driver, wherein the control circuit controls the equalizer and the precharger independently so that the precharger continues supplying the precharge potential to the first and second driving signal lines until essentially immediately before the driving signal supply circuit supplies the driving signal to the first and second driving signal lines.
摘要翻译：半导体存储器件包括至少包括第一存储器单元和第二存储单元的多个存储器单元，连接到第一存储器单元的第一位线，连接到第二存储单元的第二位线，并与第一位配对连接在第一和第二位线之间的均衡器，连接在第一和第二位线之间的放大器，连接到放大器并驱动放大器的第一驱动信号线，连接到放大器的第二驱动信号线，第一驱动信号线，用于驱动放大器并连接到第一和第二驱动信号线并且包含用于将第一和第二驱动信号线的电位预设为预定预充电电位的预充电器的驱动器和用于向第一和第二驱动信号线提供驱动信号，以及用于控制均衡器和驱动器的控制电路 r，其中控制电路独立地控制均衡器和预充电器，使得预充电器继续向第一和第二驱动信号线提供预充电电位，直到驱动信号提供电路将驱动信号提供给第一和第二驱动信号为止线条。

5. 发明授权

US6066896A Semiconductor integrated circuit device and its manufacturing method 失效
公开(公告)号：US6066896A
公开(公告)日：2000-05-23
申请号：US551
申请日：1997-12-30
申请人： Osamu Wada , Ryo Haga , Tomoaki Yabe , Shinji Miyano
发明人： Osamu Wada , Ryo Haga , Tomoaki Yabe , Shinji Miyano
IPC分类号： H01L21/768 , H01L21/82 , H01L23/528 , H01L27/10 , H01L27/118 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/528 , H01L27/118 , H01L2924/0002 , Y10S257/903
摘要： On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

6. 发明授权

US5659507A Clock synchronous type DRAM with data latch 失效
标题翻译：具有数据锁存器的时钟同步型DRAM
公开(公告)号：US5659507A
公开(公告)日：1997-08-19
申请号：US753432
申请日：1996-11-25
申请人： Tomoaki Yabe , Kenji Numata , Katsuhiko Sato , Ryo Haga , Shinji Miyano , Tohru Furuyama
发明人： Tomoaki Yabe , Kenji Numata , Katsuhiko Sato , Ryo Haga , Shinji Miyano , Tohru Furuyama
IPC分类号： G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1072 , G11C7/1078
摘要： A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate. The write circuit writes data into the data latch in synchronism with a clock signal. At the time of writing data into the memory cells, data is previously supplied to the data latch by the write circuit and latched in the data latch, and after the transfer gate control circuit controls the transfer gate to supply data to the bit line pairs from the data latch, the sense amplifier control circuit activates the sense amplifier.
摘要翻译：半导体存储器件包括存储单元阵列，行解码器，位线对，读出放大器，读出放大器控制电路，数据锁存器，传输门，传输门控制电路和写电路。存储单元阵列具有以阵列形式排列的动态存储单元。行解码器解码行地址信号以选择存储单元阵列的所需行中的一行。每个位线对连接到布置在存储单元阵列的相应列上的存储单元的每一个。读出放大器放大在配对位线上读出的数据，并将数据反馈给配对的位线以保存数据。读出放大器控制电路控制读出放大器的工作。数据锁存器锁存读出数据和写入数据。传输门在数据锁存器和读出放大器之间传送数据。传输门控制电路控制传输门。写入电路与时钟信号同步地将数据写入数据锁存器。在将数据写入存储器单元时，数据预先由写入电路提供给数据锁存器并锁存在数据锁存器中，并且在传输门控制电路控制传输门以向位线对提供数据之后数据锁存器，读出放大器控制电路激活读出放大器。

7. 发明授权

US5698876A Memory standard cell macro for semiconductor device 失效
标题翻译：用于半导体器件的内存标准单元宏
公开(公告)号：US5698876A
公开(公告)日：1997-12-16
申请号：US576477
申请日：1995-12-21
申请人： Tomoaki Yabe , Shinji Miyano , Katsuhiko Sato , Kenji Numata
发明人： Tomoaki Yabe , Shinji Miyano , Katsuhiko Sato , Kenji Numata
IPC分类号： G11C11/401 , G11C11/00 , G11C11/4074 , G11C29/14 , H01L21/82 , H01L27/02 , H01L27/10 , H01L27/118 , H01L27/108
CPC分类号： G11C29/14 , G11C11/005 , G11C11/4074 , H01L27/0207 , Y10S257/909
摘要： A semiconductor device of a memory-macro type can be designed within a short time to have a desired storage capacity, which does not occupy a large area, so as to reduce the chip cost. The semiconductor device includes a memory macro having sub-memory macros, each sub-memory macro having a DRAM memory-cell array, and a row decoder and a column decoder for selecting any desired memory-cell from the memory cell of the array. The memory macro also includes a control-section macro having a DC potential generating circuit for generating various DC potentials required to drive the sub-memory macros. At least one of the sub-memory macros is combined with the control-section macro to form the memory macro as a one-chip memory capable of storing an integral multiple of N bits.
摘要翻译：可以在短时间内设计存储器 - 宏型半导体器件以具有不占用大面积的期望的存储容量，从而降低芯片成本。半导体器件包括具有子存储器宏的存储器宏，每个子存储器宏具有DRAM存储单元阵列，以及用于从阵列的存储器单元中选择任何所需存储单元的行解码器和列解码器。存储器宏还包括具有DC电位产生电路的控制部分宏，用于产生驱动子存储器宏所需的各种DC电位。子存储器宏中的至少一个与控制部分宏组合以形成作为能够存储N位的整数倍的单片存储器的存储器宏。

8. 发明授权

US5640365A Semiconductor memory device with a decoding peripheral circuit for improving the operation frequency 失效
标题翻译：具有用于提高操作频率的解码外围电路的半导体存储器件
公开(公告)号：US5640365A
公开(公告)日：1997-06-17
申请号：US524630
申请日：1995-09-07
申请人： Keniti Imamiya , Shinji Miyano , Katsuhiko Sato , Tomoaki Yabe
发明人： Keniti Imamiya , Shinji Miyano , Katsuhiko Sato , Tomoaki Yabe
IPC分类号： G11C7/22 , G11C8/18 , G11C29/00 , G11C7/00
CPC分类号： G11C29/842 , G11C29/844 , G11C7/22 , G11C8/18
摘要： A data register that stores the data corresponding to the selected memory cell in a memory cell array is provided near the memory cell array. A decoder that selects the data from the data register starts decoding in response to an address signal accessing the memory cells in synchronization with a clock signal determining the operation period. In the first half of an operation period of the clock signal, the decoder outputs a signal in response to a signal corresponding to the address signal determined in the preceding operation period. According to the output of the decoder, the data register is selected. In the latter half of the operation period, a signal corresponding to a new address signal for the next operation period is transferred to the decoder. By doing this, the output control signal in the decoder is caused to synchronize with a signal driving an address signal, enabling the proper address to be selected without fail.
摘要翻译：在存储单元阵列附近提供将存储单元阵列中与所选存储单元对应的数据存储的数据寄存器。从数据寄存器中选择数据的解码器响应于与确定操作周期的时钟信号同步地访问存储器单元的地址信号开始解码。在时钟信号的运算周期的前半部分中，解码器响应于与前一操作周期中确定的地址信号对应的信号输出信号。根据解码器的输出，选择数据寄存器。在操作期间的后半部分，将与下一个操作期间的新的地址信号对应的信号传送到解码器。通过这样做，使解码器中的输出控制信号与驱动地址信号的信号同步，使得能够选择合适的地址。

9. 发明授权

US5890186A Memory circuit with built-in cache memory 失效
标题翻译：具有内置缓存的内存电路
公开(公告)号：US5890186A
公开(公告)日：1999-03-30
申请号：US895863
申请日：1997-07-17
申请人： Katsuhiko Sato , Shinji Miyano , Tomoaki Yabe , Tohru Furuyama
发明人： Katsuhiko Sato , Shinji Miyano , Tomoaki Yabe , Tohru Furuyama
IPC分类号： G11C11/409 , G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/407 , G11C11/34
CPC分类号： G11C7/1051 , G11C11/005
摘要： When data stored in a memory cell of a memory cell array is written into cache memory, a write signal LW is set at an "H" level. The write signal LW is input into a data-line pair initialization select circuit via an initialization control circuit, and a signal EQE is set at an "H" level in all columns. A data-line pair initialization circuit then sets the potential of the data-line pairs in all columns at the same level. When the write signal LW is input to a transfer gate via a transfer gate control circuit, the transfer gates in all columns are turned ON. The delay time of the transfer gate control circuit is the same as or greater than the delay time of the initialization control.
摘要翻译：当存储在存储单元阵列的存储单元中的数据被写入高速缓冲存储器时，写入信号LW被设置为“H”电平。写入信号LW通过初始化控制电路输入到数据线对初始化选择电路，信号EQE在所有列中被设置为“H”电平。然后，数据线对初始化电路将所有列中的数据线对的电位设置在相同的电平。当写信号LW通过传输门控制电路输入到传输门时，所有列中的传输门被接通。传输门控制电路的延迟时间与初始化控制的延迟时间相同或更大。

10. 发明授权

US5640351A Semiconductor memory circuit having data buses common to a plurality of memory cell arrays 失效
标题翻译：具有多个存储单元阵列共用的数据总线的半导体存储电路
公开(公告)号：US5640351A
公开(公告)日：1997-06-17
申请号：US601859
申请日：1996-02-15
申请人： Tomoaki Yabe , Shinji Miyano , Katsuhiko Sato , Kenji Numata
发明人： Tomoaki Yabe , Shinji Miyano , Katsuhiko Sato , Kenji Numata
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/409 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4096 , G11C7/10
摘要： According to the present invention, a data bus common to a plurality of memory cell arrays is formed by selecting a column so as to prevent a data collision from occurring. Specifically, two memory cell arrays have each of data buses in common. A column decoder is supplied with a control signal to control a column selection logic circuit. The column selection logic circuit is so controlled that the data read out to the data buses in response to the control signal is prevented from colliding with each other during the simultaneous access to the two cell arrays.
摘要翻译：根据本发明，通过选择列来形成多个存储单元阵列共用的数据总线，以防止发生数据冲突。具体地说，两个存储单元阵列共有数据总线。列解码器被提供有控制信号以控制列选择逻辑电路。列选择逻辑电路被如此控制，以便在同时访问两个单元阵列期间防止响应于控制信号读出到数据总线的数据彼此相冲突。

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