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1. 发明授权

US6066896A Semiconductor integrated circuit device and its manufacturing method 失效
公开(公告)号：US6066896A
公开(公告)日：2000-05-23
申请号：US551
申请日：1997-12-30
申请人： Osamu Wada , Ryo Haga , Tomoaki Yabe , Shinji Miyano
发明人： Osamu Wada , Ryo Haga , Tomoaki Yabe , Shinji Miyano
IPC分类号： H01L21/768 , H01L21/82 , H01L23/528 , H01L27/10 , H01L27/118 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/528 , H01L27/118 , H01L2924/0002 , Y10S257/903
摘要： On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

2. 发明授权

US06429521B1 Semiconductor integrated circuit device and its manufacturing method 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06429521B1
公开(公告)日：2002-08-06
申请号：US09531177
申请日：2000-03-21
申请人： Osamu Wada , Ryo Haga , Tomoaki Yabe , Shinji Miyano
发明人： Osamu Wada , Ryo Haga , Tomoaki Yabe , Shinji Miyano
IPC分类号： H01L2348
CPC分类号： H01L23/528 , H01L27/118 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).
摘要翻译：在半导体基板上，形成有由金属布线层（例如铝布线）形成的具有三层布线层的第一宏观单元和具有由金属布线形成的三层布线层的第二宏观单元层与第一个宏单元类似。第一宏单元形成为具有三个布线层的布线结构，尽管最初所需数量的金属布线层是两个。第一宏单元上的各层的金属布线层由与第二宏单元上的各层的金属布线层相同的材料形成。此外，各层的金属布线层形成为具有相同的膜厚度。为了将第一和第二宏单元彼此连接，形成宏布线布置在第三布线层（最上布线层）中。

3. 发明授权

US06275428B1 Memory-embedded semiconductor integrated circuit device and method for testing same 有权
标题翻译：内存式半导体集成电路器件及其测试方法
公开(公告)号：US06275428B1
公开(公告)日：2001-08-14
申请号：US09598209
申请日：2000-06-21
申请人： Ryo Fukuda , Osamu Wada , Shinji Miyano
发明人： Ryo Fukuda , Osamu Wada , Shinji Miyano
IPC分类号： G11C700
CPC分类号： G11C29/14 , G11C29/48 , G11C2207/104
摘要： There is provided a memory-embedded semiconductor integrated circuit device capable of being tested in a shorter test time. The memory-embedded semiconductor integrated circuit device includes: a logic part provided on a semiconductor substrate; a memory macro provided on the semiconductor substrate to be consolidated with the logic part; a test input terminal for inputting a test input signal; a test circuit including a test signal generator for generating an output switching signal and a test signal, which serves to carry out a test operation of the memory macro, on the basis of the test input signal, and a switching circuit for selectively outputting one of an output of the memory macro, which has been test-operated by the test signal, and the test input signal in accordance with the output switching signal; and a test output terminal for receiving an output of the switching circuit to output the output of the switching circuit to the outside.
摘要翻译：提供了一种能够在较短测试时间内测试的内存嵌入式半导体集成电路器件。存储器嵌入式半导体集成电路器件包括：设置在半导体衬底上的逻辑部分; 提供在半导体衬底上以与逻辑部分合并的存储器宏; 用于输入测试输入信号的测试输入端; 测试电路，包括用于产生输出切换信号的测试信号发生器和用于基于测试输入信号执行存储器宏的测试操作的测试信号;以及切换电路，用于选择性地输出已经由测试信号测试的存储器宏的输出和根据输出切换信号的测试输入信号; 以及测试输出端子，用于接收开关电路的输出，以将开关电路的输出输出到外部。

4. 发明授权

US08833938B2 Progressive-power spectacle lens design method 有权
标题翻译：渐进式眼镜镜片设计方法
公开(公告)号：US08833938B2
公开(公告)日：2014-09-16
申请号：US13230655
申请日：2011-09-12
申请人： Osamu Wada , Tadashi Kaga
发明人： Osamu Wada , Tadashi Kaga
IPC分类号： G02C7/02 , G02C7/06
CPC分类号： G02C7/065 , G02C7/024 , G02C7/027 , G02C7/061 , G02C2202/08
摘要： A progressive-power spectacle lens design method, the progressive-power spectacle lens including a distance portion, a near portion, and a progressive portion provided between the distance portion and the near portion, the method comprising: decreasing a distance along a principal meridian from a fitting point to a progression start point and increasing a length of a progressive corridor defined by the progression start point and a progression end point when addition power is large, whereas increasing the distance along the principal meridian from the fitting point to the progression start point and decreasing the length of the progressive corridor when the addition power is small, wherein the distance from the fitting point to the progression end point is fixed irrespective of the addition power.
摘要翻译：渐进式眼镜透镜设计方法，包括设置在距离部分和近部分之间的距离部分，近部分和渐进部分的渐进屈光力眼镜透镜，所述方法包括：沿着主子午线距离一个加速起点的拟合点，并且增加由加速开始点定义的渐进走廊的长度和加法功率大时的进展终点，而将沿着主子午线的距离从拟合点增加到加速起始点并且当相加功率较小时减小渐进走廊的长度，其中从装配点到进位终点的距离是固定的，而与加法功率无关。

5. 发明授权

US08741525B2 Resin coated carrier, two-component developer, developing device and image forming apparatus 有权
标题翻译：树脂涂层载体，双组分显影剂，显影装置和成像装置
公开(公告)号：US08741525B2
公开(公告)日：2014-06-03
申请号：US12495973
申请日：2009-07-01
申请人： Osamu Wada , Takanori Kamoto , Tadashi Iwamatsu , Nobuyuki Yoshioka , Hiroyuki Hirakawa , Yoshinori Mutoh , Takashi Hara , Hirofumi Kanda , Yoshio Ichii
发明人： Osamu Wada , Takanori Kamoto , Tadashi Iwamatsu , Nobuyuki Yoshioka , Hiroyuki Hirakawa , Yoshinori Mutoh , Takashi Hara , Hirofumi Kanda , Yoshio Ichii
IPC分类号： G03G9/00
CPC分类号： G03G9/1136 , G03G9/08755 , G03G9/09716 , G03G9/09725 , G03G9/1075 , G03G9/1139
摘要： The resin coated carrier is used with a toner in which an external additive having an average primary particle size of 50 nm or more is added to a toner particle, and has a carrier core and a resin coating layer on the surface of the carrier core. In the resin coated carrier, the following expression (1) is satisfied: 0.5≦−log {(A/C)/(B/C)}≦2.5 (1) wherein A represents a volume resistance value (Ω/cm) of the resin coated carrier in an electric field of 1000 V/cm that is obtained by conducting a stirring test, B represents a volume resistance value (Ω/cm) of the resin coated carrier in an electric field of 1000 V/cm before the stirring test, and C represents a volume resistance value (Ω/cm) of the carrier core in an electric field of 1000 V/cm.
摘要翻译：树脂涂布载体与调色剂一起使用，其中平均一次粒径为50nm以上的外部添加剂添加到调色剂颗粒中，并且在载体芯的表面上具有载体芯和树脂涂层。在树脂被覆载体中满足以下表达式（1）：0.5＆nlE; -log {（A / C）/（B / C）}＆nlE; 2.5（1）其中A表示体积电阻值（＆ cm），通过进行搅拌试验而得到的电场为1000V / cm的树脂被覆载体的B，表示在1000V / cm 2的电场中的树脂被覆载体的体积电阻值（＆amp; cm，并且C表示载体芯在1000V / cm的电场中的体积电阻值（＆amp; R g / cm）。

6. 发明授权

US08409778B2 Resin coated carrier, two-component developer, developing device and image forming apparatus 有权
标题翻译：树脂涂层载体，双组分显影剂，显影装置和成像装置
公开(公告)号：US08409778B2
公开(公告)日：2013-04-02
申请号：US12691430
申请日：2010-01-21
申请人： Osamu Wada , Tadashi Iwamatsu , Takanori Kamoto , Nobuyuki Yoshioka , Natsuki Matsuura , Nobuhiro Seki , Masatomo Hayashi
发明人： Osamu Wada , Tadashi Iwamatsu , Takanori Kamoto , Nobuyuki Yoshioka , Natsuki Matsuura , Nobuhiro Seki , Masatomo Hayashi
IPC分类号： G03G15/08
CPC分类号： G03G9/1136 , G03G9/107 , G03G2215/0607
摘要： A resin coated carrier is provided that can stably charge a toner having added thereto an external additive having a large particle size over a long period of time and can prevent blocking of a developer. The resin coated carrier satisfies the following formula (1): log(Mb/Ma)>2 (1) in which Ma is a weight average molecular weight of a silicone resin having the minimum weight average molecular weight, contained in a resin coating layer, and Mb is a weight average molecular weight of a silicone resin having the maximum weight average molecular weight, and the following formula (2) is satisfied: 0.5≦−log(A/B)≦2.5 (2) in which A is a volume resistance (Ω/cm) under electric field of 1,000 V/cm obtained by conducting a stirring test, and B is a volume resistance (Ω/cm) under electric field of 1,000 V/cm before the stirring test.
摘要翻译：提供一种树脂涂布的载体，其可以在长时间内稳定地加入具有大粒径的外部添加剂的调色剂，并且可以防止显影剂的堵塞。树脂涂布载体满足下式（1）：log（Mb / Ma）> 2（1）其中Ma是包含在树脂涂层中的具有最小重均分子量的有机硅树脂的重均分子量，Mb是具有最大重均分子量的有机硅树脂的重均分子量，满足下式（2）：0.5＆nlE; -log（A / B）＆nlE; 2.5（2）其中A 是在通过搅拌试验获得的1000V / cm的电场下的体积电阻（＆amp; OHgr / cm），B是在搅拌试验前的1000V / cm的电场下的体积电阻（＆amp; OHgr / cm）。

7. 发明授权

US08293446B2 Resin-coated carrier method of manufacturing the same, two-component developer including resin-coated carrier, developing device and image forming apparatus 有权
标题翻译：树脂涂布载体的制造方法，包括树脂涂布载体，显影装置和成像装置的双组分显影剂
公开(公告)号：US08293446B2
公开(公告)日：2012-10-23
申请号：US12769121
申请日：2010-04-28
申请人： Osamu Wada , Takanori Kamoto , Nobuyuki Yoshioka , Ayae Nagaoka , Tadashi Iwamatsu
发明人： Osamu Wada , Takanori Kamoto , Nobuyuki Yoshioka , Ayae Nagaoka , Tadashi Iwamatsu
IPC分类号： G03G9/10
CPC分类号： G03G9/1137 , G03G9/107 , G03G9/1131 , G03G9/1133 , G03G9/1136
摘要： A resin-coated carrier is provided. A resin-coated carrier includes a carrier core and a resin coating layer formed on a surface of the carrier core. The carrier core is composed of a porous material having surface fine pores formed on a surface thereof, and has an apparent density of 1.6 to 2.0 g/cm3. The resin coating layer contains cross-linked fine resin particles. Additionally, the resin-coated carrier is configured such that a volume average particle size of the cross-linked fine resin particles contained in the resin coating layer and an area average diameter of the surface fine pores satisfy a predetermined relational expression.
摘要翻译：提供树脂涂层载体。树脂涂布载体包括载体芯和形成在载体芯的表面上的树脂涂层。载体芯由具有在其表面形成的表面细孔的多孔材料构成，表观密度为1.6〜2.0g / cm 3。树脂涂层含有交联的细树脂颗粒。另外，树脂被覆载体被构造成使得包含在树脂被覆层中的交联的微粒树脂颗粒的体积平均粒径和表面细孔的面积平均直径满足预定的关系式。

8. 发明授权

US08199071B2 Color display device and color display method 有权
标题翻译：彩色显示设备和彩色显示方式
公开(公告)号：US08199071B2
公开(公告)日：2012-06-12
申请号：US13113625
申请日：2011-05-23
申请人： Osamu Wada , Junichi Nakamura
发明人： Osamu Wada , Junichi Nakamura
IPC分类号： G09G3/00
CPC分类号： G09G3/2003 , G09G3/20 , G09G3/34 , G09G3/3406 , G09G3/3413 , G09G3/346 , G09G3/3611 , G09G2310/0235 , G09G2320/0242 , G09G2320/0261 , G09G2360/18
摘要： The color display device includes a colored light generation unit for repetitively generating a plurality of colored lights in a time sequence with a predetermined frequency, and an image generation unit for processing said plurality of colored lights, so as to generate an image corresponding to each of the plurality of colored lights generated in a time sequence. The said predetermined frequency is 180 Hz or more.
摘要翻译：彩色显示装置包括用于以预定频率以时间顺序重复产生多个彩色光的彩色光产生单元，以及用于处理所述多个彩色光的图像生成单元，以便产生与每个彩色光对应的图像以时间顺序生成多个彩色光。所述预定频率为180Hz以上。

9. 发明授权

US07557400B2 Semiconductor device in which capacitance of a MOS capacitor is complemented with the capacitance of a wiring capacitor 有权
标题翻译： MOS电容器的电容与布线电容器的电容互补的半导体器件
公开(公告)号：US07557400B2
公开(公告)日：2009-07-07
申请号：US11670605
申请日：2007-02-02
申请人： Osamu Wada , Hiroaki Nakano , Hiroshi Ito , Toshimasa Namekawa , Atsushi Nakayama
发明人： Osamu Wada , Hiroaki Nakano , Hiroshi Ito , Toshimasa Namekawa , Atsushi Nakayama
IPC分类号： H01L27/108 , H01L29/00
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0222 , H01L2924/0002 , H02M3/073 , H01L2924/00
摘要： A semiconductor device has a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and a wiring capacitor which has a first comb-shaped wiring that is formed on said MOS capacitor through an interlayer insulating film, is connected to the gate electrode of said MOS capacitor, and has projecting portions projecting like comb teeth and a second comb-shaped wiring that is formed on said MOS capacitor through the interlayer insulating film, is arranged across an inter-line insulating film from the first comb-shaped wiring, is connected to the drain region and source region, and has projecting portions projecting like comb teeth, wherein the projecting portions of the second comb-shaped wiring are arranged alternately with the projecting portions of the first comb-shaped wiring and arranged perpendicularly to a channel direction connecting the drain region and source region of said MOS capacitor.
摘要翻译：半导体器件具有其中共同连接漏极区域和MOS结构的源极区域的MOS电容器，并且在共同连接的漏极区域/源极区域和MOS结构的栅极电极之间形成电容; 以及具有通过层间绝缘膜形成在所述MOS电容器上的第一梳状布线的布线电容器连接到所述MOS电容器的栅电极，并且具有突出部分，如梳齿形状突出，第二梳状通过层间绝缘膜在所述MOS电容器上形成的布线跨越与第一梳状布线的线间绝缘膜布置，连接到漏区和源极区，并且具有突出部分如梳齿突出，其中，所述第二梳状布线的突出部分与所述第一梳状布线的突出部分交替布置，并且垂直于连接所述MOS电容器的漏极区域和源极区域的沟道方向布置。

10. 发明授权

US07542055B2 Image display system, projector, information storage medium, and image processing method 有权
标题翻译：图像显示系统，投影仪，信息存储介质，图像处理方法
公开(公告)号：US07542055B2
公开(公告)日：2009-06-02
申请号：US10343429
申请日：2002-05-29
申请人： Hideki Matsuda , Osamu Wada
发明人： Hideki Matsuda , Osamu Wada
IPC分类号： G09G5/10 , G06K9/00 , G03B21/00
CPC分类号： H04N9/69 , G09G1/285 , G09G3/002 , G09G5/02 , G09G5/06 , G09G2320/0285 , G09G2320/0626 , G09G2320/0666 , G09G2320/0693 , G09G2360/144 , H04N5/202 , H04N5/58 , H04N9/3182 , H04N9/3194 , H04N9/73 , H04N17/045
摘要： An image display system that performs grayscale correction in accordance with the on-site environment, to display an image, is provided with: a calibration signal generation section (150) that generates calibration signals for displaying each of first and second grayscale correction images having two grayscale values of a single color, a color-light sensor (60) that measures luminance values under an ideal environment and the on-site environment for each of the first and the second grayscale correction images projected on a screen, a 1D-LUT generation section (140) that generates a 1D-LUT based on the luminance values measured by the color-light sensor (60), and a grayscale correction section (170) that stores the 1D-LUT generated by the 1D-LUT generation section (140) and performs grayscale correction.
摘要翻译：一种根据现场环境执行灰度校正以显示图像的图像显示系统具有：校准信号生成部分（150），其生成用于显示具有两个第一和第二灰度校正图像的每个的校准信号单个颜色的灰度值，在理想环境下测量亮度值的色光传感器（60）和投影在屏幕上的第一和第二灰阶校正图像中的每一个的现场环境，1D-LUT生成基于由色光传感器（60）测量的亮度值生成1D-LUT的区段（140）;以及存储由1D-LUT生成部（140）生成的1D-LUT的灰度校正部（170））并执行灰度校正。

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