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1. 发明申请

US20140002976A1 RECESSED BOTTOM-ELECTRODE CAPACITORS AND METHODS OF ASSEMBLING SAME 审中-公开
标题翻译：接触底电极电容器及其组装方法
公开(公告)号：US20140002976A1
公开(公告)日：2014-01-02
申请号：US13997974
申请日：2011-11-10
申请人： Ruth A. Brain , Joseph M. Steigerwald
发明人： Ruth A. Brain , Joseph M. Steigerwald
IPC分类号： H01L49/02 , H01L27/108 , G06F1/16
CPC分类号： H01L28/40 , G06F1/16 , H01L27/108 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： A capacitor-over-bitline structure includes a bottom electrode that has an open vessel form factor. The bottom-electrode form factor includes a floor, rectilinear sidewalls, and a rim that defines the topmost feature. A capacitor dielectric film contacts and covers the floor, the sidewalls, and the rim. A top electrode has a convex form factor that complements the concave bottom-electrode form factor. A process of forming the capacitor-over-bitline structure by spinning on a reflowable sacrificial material such as an oxide that covers both logic and memory portions of a semiconductive device, followed by a polish-back process and a recessing etch of the bottom electrode.
摘要翻译：电容器 - 位线结构包括具有开放容器外形的底部电极。底部电极形状因子包括底板，直线侧壁和限定最顶端特征的边缘。电容器电介质膜接触并覆盖地板，侧壁和边缘。顶部电极具有补充凹底电极形状因子的凸形形状因子。通过在可覆盖的牺牲材料（例如覆盖半导体器件的逻辑和存储器部分的氧化物）上旋转形成电容器 - 位线结构的过程，接着是底部电极的抛光处理和凹陷蚀刻。

2. 发明申请

US20140001598A1 ATOMIC LAYER DEPOSITION (ALD) OF TAALC FOR CAPACITOR INTEGRATION 审中-公开
标题翻译：用于电容器积分的TAALC的原子层沉积（ALD）
公开(公告)号：US20140001598A1
公开(公告)日：2014-01-02
申请号：US13977550
申请日：2011-12-21
申请人： Nick Lindert , Ruth A. Brain , Joseph M. Steigerwald , Timothy E. Glassman , Andre Baran
发明人： Nick Lindert , Ruth A. Brain , Joseph M. Steigerwald , Timothy E. Glassman , Andre Baran
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , C23C16/0281 , C23C16/045 , C23C16/32 , C23C16/45525
摘要： Atomic layer deposition (ALD) of TaAlC for capacitor integration is generally described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in at least one of the dielectric layers, the MIM capacitor includes an electrode having a conformal layer of TaAlC and the MIM capacitor is electrically coupled to one or more of the semiconductor devices. Other embodiments are also disclosed and claimed.
摘要翻译：通常描述用于电容器集成的TaAlC的原子层沉积（ALD）。例如，半导体结构包括设置在基板中或上方的多个半导体器件。一个或多个电介质层设置在多个半导体器件的上方。金属绝缘体金属（MIM）电容器设置在至少一个电介质层中，MIM电容器包括具有保形层TaAlC的电极，并且MIM电容器电耦合到一个或多个半导体器件。还公开并要求保护其他实施例。

3. 发明授权

US08933564B2 Landing structure for through-silicon via 有权
标题翻译：穿硅通孔的着陆结构
公开(公告)号：US08933564B2
公开(公告)日：2015-01-13
申请号：US13725917
申请日：2012-12-21
申请人： Christopher M. Pelto , Ruth A. Brain , Kevin J. Lee , Gerald S. Leatherman
发明人： Christopher M. Pelto , Ruth A. Brain , Kevin J. Lee , Gerald S. Leatherman
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76879 , H01L21/76898 , H01L23/522 , H01L23/5226 , H01L2224/16225 , H01L2924/15311
摘要： Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述与使用互连层的互连结构形成用于穿硅通孔（TSV）的着陆结构相关联的技术和配置。在实施例中，一种装置包括具有第一表面和与第一表面相对的第二表面的半导体衬底，设置在半导体衬底的第一表面上的器件层，器件层包括一个或多个晶体管器件，布置的互连层在所述器件层上，所述互连层包括多个互连结构以及设置在所述第一表面和所述第二表面之间的一个或多个穿硅通孔，其中所述多个互连结构包括互连结构，所述互连结构与所述一个或多个 TSV并且被配置为提供一个或多个TSV的一个或多个相应的着陆结构。可以描述和/或要求保护其他实施例。

4. 发明申请

US20140175651A1 LANDING STRUCTURE FOR THROUGH-SILICON VIA 有权
标题翻译：通过硅的接地结构
公开(公告)号：US20140175651A1
公开(公告)日：2014-06-26
申请号：US13725917
申请日：2012-12-21
申请人： Christopher M. Pelto , Ruth A. Brain , Kevin J. Lee , Gerald S. Leatherman
发明人： Christopher M. Pelto , Ruth A. Brain , Kevin J. Lee , Gerald S. Leatherman
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76879 , H01L21/76898 , H01L23/522 , H01L23/5226 , H01L2224/16225 , H01L2924/15311
摘要： Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述与使用互连层的互连结构形成用于穿硅通孔（TSV）的着陆结构相关联的技术和配置。在实施例中，一种装置包括具有第一表面和与第一表面相对的第二表面的半导体衬底，设置在半导体衬底的第一表面上的器件层，器件层包括一个或多个晶体管器件，布置的互连层在所述器件层上，所述互连层包括多个互连结构以及设置在所述第一表面和所述第二表面之间的一个或多个穿硅通孔，其中所述多个互连结构包括互连结构，所述互连结构与所述一个或多个 TSV并且被配置为提供一个或多个TSV的一个或多个相应的着陆结构。可以描述和/或要求保护其他实施例。

5. 发明授权

US06958547B2 Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs 有权
标题翻译：互连结构包含导电的无电沉积蚀刻停止层，衬里层和通孔塞
公开(公告)号：US06958547B2
公开(公告)日：2005-10-25
申请号：US10446749
申请日：2003-05-28
申请人： Valery M. Dubin , Chin-Chang Cheng , Makarem Hussein , Phi L. Nguyen , Ruth A. Brain
发明人： Valery M. Dubin , Chin-Chang Cheng , Makarem Hussein , Phi L. Nguyen , Ruth A. Brain
IPC分类号： H01L21/288 , H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76807 , H01L21/76838 , H01L21/76849 , H01L21/76852 , H01L21/76864 , H01L21/76868 , H01L21/76874 , H01L21/76879 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.
摘要翻译：公开了用于制造互连结构的多级互连结构和方法。互连结构可以包含互连线，在互连线上形成的无电沉积金属层，在金属层上形成的通孔，以及形成在通孔上的第二互连线。通常，金属层含有钴或镍合金，并提供用于形成对应于通孔的开口的蚀刻停止层。金属层可以为下面的互连线提供保护，并且可以代替传统的保护性介电层。金属层是导电的，而不是电介质，并且提供用于通孔和互连线之间的电流的分流。在互连结构中也可以使用类似的金属层，如通过衬垫层和通孔塞。

6. 发明授权

US5851319A Method and apparatus for selectively annealing heterostructures using microwaves 失效
标题翻译：使用微波选择性退火异质结构的方法和装置
公开(公告)号：US5851319A
公开(公告)日：1998-12-22
申请号：US911304
申请日：1997-08-14
申请人： Harry A. Atwater , Ruth A. Brain , Martin B. Barmatz
发明人： Harry A. Atwater , Ruth A. Brain , Martin B. Barmatz
IPC分类号： H01L21/3105 , H01L21/321 , H01L21/324
CPC分类号： H01L21/31051 , H01L21/32115
摘要： The present invention discloses a process for selectively annealing heterostructures using microwaves. A heterostructure, comprised of a material having higher microwave absorption and a material having lower microwave absorption, is exposed to microwaves in the cavity. The higher microwave absorbing material absorbs the microwaves and selectively heats while the lower microwave absorbing material absorbs small amounts of microwaves and minimally heats. The higher microwave absorbing material is thereby annealed onto the less absorbing material which is thermally isolated.
摘要翻译：本发明公开了一种使用微波选择性退火异质结构的方法。由具有较高微波吸收的材料和具有较低微波吸收的材料组成的异质结构暴露于空腔中的微波。较高的微波吸收材料吸收微波并选择性加热，而较低的微波吸收材料吸收少量的微波和最少的热量。因此，较高的微波吸收材料被退火到热隔离的较少吸收材料上。

7. 发明申请

US20130279102A1 ETCHSTOP LAYERS AND CAPACITORS 有权
公开(公告)号：US20130279102A1
公开(公告)日：2013-10-24
申请号：US13977647
申请日：2011-11-03
申请人： Ruth A. Brain
发明人： Ruth A. Brain
IPC分类号： H01L49/02 , G06F1/18
CPC分类号： H01L28/60 , G06F1/184 , H01L21/02148 , H01L21/0217 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/31144 , H01L21/76829 , H01L21/76832 , H01L21/76877 , H01L23/5223 , H01L23/5226 , H01L23/5283 , H01L23/53228 , H01L23/5329 , H01L27/10805 , H01L27/10814 , H01L27/1085 , H01L27/10852 , H01L27/10885 , H01L28/40 , H01L28/90 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.

8. 发明授权

US09054068B2 Etchstop layers and capacitors 有权
标题翻译：蚀刻层和电容器
公开(公告)号：US09054068B2
公开(公告)日：2015-06-09
申请号：US13977647
申请日：2011-11-03
申请人： Ruth A. Brain
发明人： Ruth A. Brain
IPC分类号： H05K1/00 , H01L49/02 , H01L21/311 , H01L23/522 , G06F1/18 , H01L21/768
CPC分类号： H01L28/60 , G06F1/184 , H01L21/02148 , H01L21/0217 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/31144 , H01L21/76829 , H01L21/76832 , H01L21/76877 , H01L23/5223 , H01L23/5226 , H01L23/5283 , H01L23/53228 , H01L23/5329 , H01L27/10805 , H01L27/10814 , H01L27/1085 , H01L27/10852 , H01L27/10885 , H01L28/40 , H01L28/90 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.
摘要翻译：提供集成电路器件的电容结构。电容器包括邻近密集或高密度的蚀刻层。致密的或高密度的蚀刻阻挡层是例如高k材料。电容器例如是金属绝缘体金属（MIM）电容器，并且在DRAM（动态随机存取存储器）和eDRAM（嵌入式动态随机存取存储器）结构中是有用的。

9. 发明申请

US20130320564A1 AVD HARDMASK FOR DAMASCENE PATTERNING 有权
公开(公告)号：US20130320564A1
公开(公告)日：2013-12-05
申请号：US13995133
申请日：2011-12-29
申请人： Ruth A. Brain , Kevin J. Fischer , Michael A. Childs
发明人： Ruth A. Brain , Kevin J. Fischer , Michael A. Childs
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L23/5329 , H01L21/311 , H01L21/31144 , H01L21/76802 , H01L21/76807 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
摘要翻译：一种包括在集成电路结构的接触点上形成介电层的方法; 在所述电介质层的表面上形成包括电介质材料的硬掩模; 以及使用所述硬掩模作为图案在所述电介质层中形成至少一个通孔到所述接触点。一种包括电路基板的装置，包括至少一个包括接触点的活性层; 所述至少一个有源层上的介电层; 包括其中具有用于互连材料的至少一个开口的电介质材料的硬掩模; 以及在硬掩模的至少一个开口中并通过介电层到接触点的互连材料。

10. 发明授权

US09502281B2 AVD hardmask for damascene patterning 有权
标题翻译：用于镶嵌图案的AVD硬掩模
公开(公告)号：US09502281B2
公开(公告)日：2016-11-22
申请号：US13995133
申请日：2011-12-29
申请人： Ruth A. Brain , Kevin J. Fischer , Michael A. Childs
发明人： Ruth A. Brain , Kevin J. Fischer , Michael A. Childs
IPC分类号： H01L21/768 , H01L23/498 , H01L21/311
CPC分类号： H01L23/5329 , H01L21/311 , H01L21/31144 , H01L21/76802 , H01L21/76807 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having at least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
摘要翻译：一种包括在集成电路结构的接触点上形成介电层的方法; 在所述电介质层的表面上形成包括电介质材料的硬掩模; 以及使用所述硬掩模作为图案在所述电介质层中形成至少一个通孔到所述接触点。一种包括电路基板的装置，包括至少一个包括接触点的活性层; 所述至少一个有源层上的介电层; 包括其中具有用于互连材料的至少一个开口的电介质材料的硬掩模; 以及在硬掩模的至少一个开口中并通过介电层到接触点的互连材料。

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