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1. 发明授权

US5683925A Manufacturing method for ROM array with minimal band-to-band tunneling 失效
标题翻译：具有最小带到带隧道的ROM阵列的制造方法
公开(公告)号：US5683925A
公开(公告)日：1997-11-04
申请号：US665150
申请日：1996-06-13
申请人： Rustom F. Irani , Reza Kazerounian , Mark Michael Nelson
发明人： Rustom F. Irani , Reza Kazerounian , Mark Michael Nelson
IPC分类号： H01L21/8246
CPC分类号： H01L27/112 , Y10S148/116 , Y10S438/981
摘要： A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) etching the ROM oxide layer only from the periphery area as per a later-removed core protect mask, d) providing a gate oxide layer over the entirety of the ROM array, e) laying down polysilicon rows in the core area as per a polysilicon mask and f) implanting a ROM implant into selected areas of the core area, thereby to produce turned off core transistors. The thickness of the gate oxide layer and the ROM oxide layer are independent of each other.
摘要翻译：描述了一种制造ROM阵列以最小化频带隧穿的方法。该方法包括以下步骤：a）根据稍后去除的位线掩模将位线注入衬底的芯区域，b）在整个衬底上提供ROM氧化层，c）蚀刻ROM氧化物层 d）在ROM阵列整体上提供栅极氧化层，e）根据多晶硅掩模放置芯区域中的多晶硅行，以及f）植入一个 ROM注入核心区域的选定区域，从而产生截止的核心晶体管。栅极氧化物层和ROM氧化物层的厚度彼此独立。

2. 发明授权

US5910016A Scalable EPROM array 失效
标题翻译：可扩展EPROM阵列
公开(公告)号：US5910016A
公开(公告)日：1999-06-08
申请号：US806559
申请日：1997-02-25
申请人： Reza Kazerounian , Rustom F. Irani , Boaz Eitan
发明人： Reza Kazerounian , Rustom F. Irani , Boaz Eitan
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115
摘要： An electrically programmable read-only memory (EPROM) array having self-aligned thick oxide isolation units, and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin oxide elements are self-aligned to the first polysilicon strip. The thin oxide and the first and second polysilicon strips form a select transistor. The thick oxide and the first and second polysilicon strips form a novel self-aligned thick oxide isolation unit.
摘要翻译：公开了一种具有自对准厚氧化物隔离单元的电可编程只读存储器（EPROM）阵列和用于制造EPROM阵列的方法。 EPROM阵列由具有EPROM单元和控制区域的EPROM区域形成，每个EPROM区域两个。每个控制区域包括至少一行，并且每行包括第一多晶硅条，位于第一多晶硅条的顶部并垂直于第一多晶硅条的第二多晶硅条，以及在第一多晶硅条下面交替的厚的和薄的氧化物元件。厚且薄的氧化物元件与第一多晶硅条自对准。薄氧化物和第一和第二多晶硅条形成选择晶体管。厚氧化物和第一和第二多晶硅条形成新的自对准厚氧化物隔离单元。

3. 发明授权

US5623443A Scalable EPROM array with thick and thin non-field oxide gate insulators 失效
标题翻译：具有厚而薄的非场氧化物栅极绝缘体的可扩展EPROM阵列
公开(公告)号：US5623443A
公开(公告)日：1997-04-22
申请号：US212165
申请日：1994-03-11
申请人： Reza Kazerounian , Rustom F. Irani , Boaz Eitan
发明人： Reza Kazerounian , Rustom F. Irani , Boaz Eitan
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115
摘要： An electrically programmable read-only memory (EPROM) array having self-aligned thick oxide isolation units, and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin oxide elements are self-aligned to the first polysilicon strip. The thin oxide and the first and second polysilicon strips form a select transistor. The thick oxide and the first and second polysilicon strips form a novel self-aligned thick oxide isolation unit.
摘要翻译：公开了一种具有自对准厚氧化物隔离单元的电可编程只读存储器（EPROM）阵列和用于制造EPROM阵列的方法。 EPROM阵列由具有EPROM单元和控制区域的EPROM区域形成，每个EPROM区域两个。每个控制区域包括至少一行，并且每行包括第一多晶硅条，位于第一多晶硅条的顶部并垂直于第一多晶硅条的第二多晶硅条，以及在第一多晶硅条下面交替的厚的和薄的氧化物元件。厚且薄的氧化物元件与第一多晶硅条自对准。薄氧化物和第一和第二多晶硅条形成选择晶体管。厚氧化物和第一和第二多晶硅条形成新的自对准厚氧化物隔离单元。

4. 发明授权

US5151375A EPROM virtual ground array 失效
标题翻译： EPROM虚拟接地阵列
公开(公告)号：US5151375A
公开(公告)日：1992-09-29
申请号：US537553
申请日：1990-06-13
申请人： Reza Kazerounian , Boaz Eitan , Rustom F. Irani
发明人： Reza Kazerounian , Boaz Eitan , Rustom F. Irani
IPC分类号： H01L21/8247 , H01L23/528 , H01L23/535
CPC分类号： H01L27/11521 , H01L23/528 , H01L23/535 , H01L2924/0002
摘要： An electrically programmable read only memory contains alternating metal bit lines and diffused bit lines. Each diffused bit line is broken into a plurality of segments. Each of the segments of the diffused bit line comprises a virtual source. A multiplicity of floating gate transistors are arranged in rows and columns. The floating gate transistors in each column are divided into M groups of N floating gate transistors each. The floating gate transistors in the n.sup.th and the (n+1).sup.th columns, where n is an odd integer given by 1.ltoreq.n.ltoreq.N and (N+1) is the maximum number of columns in the array are connected to the segments of one diffused bit line placed between the n.sup.th and the (n+1).sup.th columns. At least one first transfer transistor is arranged to connect one segment comprising a virtual source to a first metal bit line. The first metal bit line functions as the source for the N floating gate transistors in the (n+1).sup.th column connected to said one segment. At least one second transfer transistor connects the same one segment comprising a virtual source to a second metal bit line. The second metal bit line functions as a source for the N floating gate transistors in the n.sup.th column connected to said one segment. The removal of each select transistor from the cell where it previously resided in series with its corresponding floating gate transistor, and the combining of a plurality of select transistors into one select transistor substantially reduces the area taken by each memory cell in the array.
摘要翻译：电可编程只读存储器包含交替的金属位线和扩散位线。每个扩散位线被分解成多个段。扩散位线的每个段包括虚拟源。多个浮栅晶体管以行和列布置。每列中的浮栅晶体管分为M组N个浮栅晶体管。第n和第（n + 1）列中的浮置栅极晶体管，其中n是由1

5. 发明授权

US6055203A Row decoder 失效
标题翻译：行解码器
公开(公告)号：US6055203A
公开(公告)日：2000-04-25
申请号：US974007
申请日：1997-11-19
申请人： Manu Agarwal , Manik Advani , Reza Kazerounian
发明人： Manu Agarwal , Manik Advani , Reza Kazerounian
IPC分类号： G11C8/10 , G11C8/00 , G11C7/00
CPC分类号： G11C8/10
摘要： A row decoder for controlling a plurality of selectable word-lines has one control line per block of N word-lines, K select lines, at least one disable line and one word-line driver per word-line. Each control line is activatable during a charge period and during an initial portion of a discharge period. Each select line is selectably high during the charge period. The disable line is active during the discharge period. Each driver includes an access transistor and a discharge transistor. The access transistor is located at one end of its word-line and the discharge transistor is connected at the other end. The access transistor is controlled by one control line and is connected between one select line and the word-line. The discharge transistor is controlled by one disable signal and is connected between the word-line and a ground supply.
摘要翻译：用于控制多个可选择字线的行解码器在每个N个字线，K个选择线，至少一个禁用行和每个字线的一个字线驱动器的块中具有一个控制线。每个控制线可在充电期间和放电期的初始部分期间激活。每个选择线在充电期间可选择高。禁用线在放电期间有效。每个驱动器包括存取晶体管和放电晶体管。存取晶体管位于其字线的一端，放电晶体管在另一端连接。存取晶体管由一条控制线控制，并连接在一条选择线和字线之间。放电晶体管由一个禁用信号控制，并连接在字线和地电源之间。

6. 发明授权

US5949711A Dual bit memory cell 失效
标题翻译：双位存储单元
公开(公告)号：US5949711A
公开(公告)日：1999-09-07
申请号：US936849
申请日：1997-09-24
申请人： Reza Kazerounian
发明人： Reza Kazerounian
IPC分类号： G11C11/56 , G11C16/04
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , G11C2211/5612
摘要： A dual bit memory cell includes a substrate, a gate unit and left and right diffusions implanted into the substrate on the outer sides of the gate unit such that a channel exists under the gate unit and between the left and right diffusions. The gate unit includes a control gate and left and right separately programmable floating gates located on the left and right sides of the control gate. Each floating gate controls a short portion of the channel. The left diffusion acts as a drain and the right diffusion acts as a source when reading the value stored in the right floating gate and the right diffusion acts as a drain and the left diffusion as a source when reading the value stored in the left floating gate. In one embodiment, the floating gates are formed of polysilicon spacers.
摘要翻译：双位存储单元包括衬底，栅极单元以及注入到栅极单元的外侧上的衬底中的左右扩散，使得沟道存在于栅极单元之下以及左右扩散之间。门单元包括位于控制门的左侧和右侧的控制栅极和左右分开可编程的浮动栅极。每个浮动门控制通道的一小部分。左扩散作为漏极，当读取存储在右浮栅中的值时，右扩散充当源，而当读出存储在左浮栅中的值时，右扩散充当漏极，而左扩散作为源。在一个实施例中，浮置栅极由多晶硅间隔物形成。

7. 发明授权

US5557124A Flash EEPROM and EPROM arrays with select transistors within the bit line pitch 失效
公开(公告)号：US5557124A
公开(公告)日：1996-09-17
申请号：US212176
申请日：1994-03-11
申请人： Anirban Roy , Reza Kazerounian
发明人： Anirban Roy , Reza Kazerounian
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115
摘要： Flash EEPROM array and EPROM arrays are described. The EEPROM array has EEPROM areas with arrays of EEPROM transistors, at least one control area per EEPROM area and columns of a first polysilicon layer traversing the EEPROM and control areas. The columns are divided into even and odd columns. Each control area is divided into upper, middle and lower areas and each control area includes the following: a) within the middle area, cross-lines of the first polysilicon extending from each even to the next odd column; b) four rows of a second polysilicon layer, laid down after the columns and cross-lines of the first polysilicon layer within the control areas are removed; and c) isolating oxide elements laid down prior to the first polysilicon layer and self-aligned to it before it is removed. The isolating oxide elements are located under every odd column in the upper area, under each column in the middle area, under each odd column in one row of the lower area and under each even column in the other row of the lower area. Bit line select and erase select rows are in the upper and middle areas, respectively, and two column select rows are in the lower area. Erase select transistors are formed at the intersections of the removed cross-lines with the erase select row of second polysilicon, bit line select transistors are formed at the intersections of removed even columns with the bit line select row of second polysilicon, and column select transistors are formed at intersections of the column select rows of second polysilicon with the removed columns wherever no isolating oxide elements exist. The EPROM array has a similar structure but does not include the erase select transistors. The select transistors are n-channel transistors each formed of a) a channel, b) two diffusion bit lines bordering the channel and aligned to a first, subsequently removed, polysilicon layer and c) a second polysilicon layer extending between and over the two diffusion bit lines.

8. 发明授权

US4758869A Nonvolatile floating gate transistor structure 失效
标题翻译：非易失性浮栅晶体管结构
公开(公告)号：US4758869A
公开(公告)日：1988-07-19
申请号：US902236
申请日：1986-08-29
申请人： Boaz Eitan , Reza Kazerounian
发明人： Boaz Eitan , Reza Kazerounian
IPC分类号： H01L21/8247 , H01L21/314 , H01L29/788 , H01L29/792 , H01L29/78 , H01L27/14 , H01L29/04 , H01L29/34
CPC分类号： H01L29/7885
摘要： A field effect transistor includes a source region, a drain region, and a channel region formed in a semiconductor substrate and a floating gate and a control gate formed over the substrate. An opaque cover (typically aluminum) is formed over but electrically insulated from the transistor to prevent light from striking and affecting the electrical charge on the floating gate. The periphery of the opaque cover ohmically contacts the semiconductor substrate, thereby limiting the amount of light reaching the floating gate, except where the source and drain extend inwardly beyond the periphery of the opaque cover. The control gate extends over a portion of the substrate surrounding the transistor, and helps hinder light from reaching the floating gate. In addition, semiconductor material formed concurrently with the control gate extends over the source and drain regions, thereby providing additional shading.
摘要翻译：场效应晶体管包括源区域，漏极区域和形成在半导体衬底中的沟道区域，以及形成在衬底上的浮置栅极和控制栅极。在晶体管上形成不透明的盖（通常为铝），但与电极绝缘，以防止光线撞击并影响浮动栅极上的电荷。不透明盖的周边与欧姆接触半导体衬底，从而限制到达浮动栅极的光量，除了源极和漏极向内延伸超出不透明盖的周边。控制栅极延伸在围绕晶体管的衬底的一部分上，并且有助于阻止光到达浮动栅极。此外，与控制栅同时形成的半导体材料在源极和漏极区域上延伸，从而提供额外的阴影。

9. 发明授权

US5327378A Easily manufacturable compact EPROM 失效
标题翻译：易于制造的紧凑型EPROM
公开(公告)号：US5327378A
公开(公告)日：1994-07-05
申请号：US846183
申请日：1992-03-04
申请人： Reza Kazerounian
发明人： Reza Kazerounian
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , G11C11/34
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115
摘要： An EPROM array comprises a plurality of floating gate memory cell transistors and a multiplicity of floating gate select transistors arranged so that at least one select transistor controls the current to a group of floating gate memory cell transistors. Each floating gate select transistor remains unprogrammed or substantially unprogrammed even though the floating gate memory cell transistors in the memory array are selectively programmed to store information. The use of floating gate transistors for both memory cell transistors and select transistors simplifies the manufacturing process and improves yield.
摘要翻译： EPROM阵列包括多个浮动栅极存储单元晶体管和多个浮置栅极选择晶体管，其布置成使得至少一个选择晶体管将电流控制到一组浮动栅极存储单元晶体管。即使存储器阵列中的浮动栅极存储单元晶体管被选择性地编程以存储信息，每个浮置栅极选择晶体管保持未编程或基本上未编程。用于存储单元晶体管和选择晶体管的浮栅晶体管简化了制造工艺并提高了产量。

10. 发明授权

US5014097A On-chip high voltage generator and regulator in an integrated circuit 失效
标题翻译：集成电路中的片上高压发生器和稳压器
公开(公告)号：US5014097A
公开(公告)日：1991-05-07
申请号：US137782
申请日：1987-12-24
申请人： Reza Kazerounian , Syed Ali , Boaz Eitan
发明人： Reza Kazerounian , Syed Ali , Boaz Eitan
IPC分类号： G11C16/30 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H02M3/07
CPC分类号： H01L27/11526 , G11C16/30 , H01L27/11546 , H02M3/073 , H01L27/105 , H01L27/115
摘要： An EEPROM constructed in accordance with our invention includes a voltage multiplier for generating an erase voltage and a voltage regulator circuit for controlling the magnitude of the erase voltage. The voltage regulator circuit includes a capacitive voltage divider for providing a first voltage proportional to the erase voltage, a reference voltage lead for providing a reference voltage and a control circuit for controlling the voltage multipler circuit so that if the first voltage is less than the reference voltage, the voltage multiplier circuit will increase the erase voltage, but if the first voltage is greater than the reference voltage, the voltage multiplier will not continue to increase the erase voltage. The voltage multiplier includes novel capacitors and transistors constructed using standard EEPROM processing to withstand high voltages without breaking down.

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