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1. 发明授权

US06265729B1 Method for detecting and characterizing plasma-etch induced damage in an integrated circuit 失效
标题翻译：用于检测和表征集成电路中的等离子体蚀刻引起的损伤的方法
公开(公告)号：US06265729B1
公开(公告)日：2001-07-24
申请号：US09277338
申请日：1999-03-26
申请人： Mark Michael Nelson , Subhash Madhukar Deshmukh
发明人： Mark Michael Nelson , Subhash Madhukar Deshmukh
IPC分类号： H01L2358
CPC分类号： H01L22/34 , H01L22/12
摘要： Characterization of plasma-induced damage in semiconductor manufacturing has long been considered unimportant because the damage had no discernible effect on circuit performance. With increasing transistor counts on an integrated circuit, the damage-induced parasitics are becoming increasingly important. Electrical characterization of such effects provides a far more sensitive method for determining the extent of damage and the effectiveness of efforts to repair the damage. A measurement of diode leakage current through a plasma-etch effect test diode which is formed completely within an active device region, removed from field oxide regions quantifies the extent of damage created by a plasma and the effectiveness of a repair technique that may be applied to the process.
摘要翻译：长期以来，半导体制造中等离子体引起的损伤的表征被认为是不重要的，因为损伤对电路性能没有明显的影响。随着集成电路中晶体管数量的增加，损伤引起的寄生效应变得越来越重要。这种影响的电气特性提供了一种更加敏感的方法来确定损伤的程度和修复损坏的努力的有效性。通过等离子蚀刻效应测试二极管的二极管泄漏电流的测量，其完全在活性器件区域内形成，从场氧化物区域移除，量化了由等离子体产生的损伤程度以及修复技术的有效性，可用于的过程。

2. 发明授权

US5838046A Operating method for ROM array which minimizes band-to-band tunneling 失效
标题翻译： ROM阵列的操作方法，使带通隧道最小化
公开(公告)号：US5838046A
公开(公告)日：1998-11-17
申请号：US665136
申请日：1996-06-13
申请人： Rustom F. Irani , Boaz Eitan , Mark Michael Nelson , Larry Willis Petersen
发明人： Rustom F. Irani , Boaz Eitan , Mark Michael Nelson , Larry Willis Petersen
IPC分类号： G11C17/12 , H01L29/76
CPC分类号： G11C17/12
摘要： A read only memory (ROM) array is disclosed which includes a) a voltage supply providing an operating voltage level, b) a plurality of word-lines, c) a multiplicity of ROM transistors, and d) a word-line clamper. The ROM transistors are divided into turned on and turned off transistors. Each ROM transistor has a gate connected to one of the word-lines, a gate oxide beneath the gate, whose thickness is less than 250 .ANG., and a channel beneath the gate oxide. The turned off transistors additionally have a ROM implant in their channel whose dosage is no larger than the amount which generates a predetermined desired minimal band-to-band tunneling current The ROM implant and gate oxide thickness define a threshold voltage for the tamed off tranistors, the threshold voltage being less than the operating voltage level. The word-line damper provides a word-line voltage to each of the word-lines, the word-line voltage being clamped to a voltage level no higher than the threshold voltage of the turned off transistor.
摘要翻译：公开了一种只读存储器（ROM）阵列，其包括a）提供工作电压电平的电压源，b）多个字线，c）多个ROM晶体管，以及d）字线钳位器。 ROM晶体管分为导通和截止晶体管。每个ROM晶体管具有连接到字线之一的栅极，栅极下方的栅极氧化物，其厚度小于250，栅极氧化物下方的沟道。关闭晶体管另外在其通道中具有ROM植入物，其剂量不大于产生预定的期望的最小带 - 带隧穿电流的量。ROM注入和栅极氧化物厚度限定了驯化的晶体管的阈值电压，阈值电压小于工作电压电平。字线阻尼器对每个字线提供字线电压，字线电压被钳位到不高于截止晶体管的阈值电压的电压电平。

3. 发明授权

US08394700B2 Device including memory array and method thereof 有权
标题翻译：包括存储器阵列的装置及其方法
公开(公告)号：US08394700B2
公开(公告)日：2013-03-12
申请号：US12765731
申请日：2010-04-22
申请人： Gregory James Scott , Mark Michael Nelson , Thierry Coffi Herve Yao
发明人： Gregory James Scott , Mark Michael Nelson , Thierry Coffi Herve Yao
IPC分类号： H01L21/336
CPC分类号： H01L27/11531 , H01L27/11521 , H01L27/11526 , H01L29/66825 , H01L29/7881
摘要： An electronic device includes a first memory cell and a second memory cell, of a nonvolatile memory array. The first memory cell includes a body region, a gate structure, a source region, and a drain region. The second memory cell includes a body region, a gate structure, a source region, and a drain region. In one embodiment, the body of the second memory cell is physically isolated from the body region of the first memory cell. A bitline segment is electrically connected to the drain region of the first memory cell and to the drain region of the second memory cell.
摘要翻译：电子设备包括非易失性存储器阵列的第一存储单元和第二存储单元。第一存储单元包括主体区域，栅极结构，源极区域和漏极区域。第二存储单元包括主体区域，栅极结构，源极区域和漏极区域。在一个实施例中，第二存储器单元的主体与第一存储单元的主体区域物理隔离。位线段电连接到第一存储单元的漏极区域和第二存储单元的漏极区域。

4. 发明申请

US20110260232A1 DEVICE INCLUDING MEMORY ARRAY AND METHOD THEREOF 有权
标题翻译：包括存储器阵列的装置及其方法
公开(公告)号：US20110260232A1
公开(公告)日：2011-10-27
申请号：US12765731
申请日：2010-04-22
申请人： Gregory James Scott , Mark Michael Nelson , Thierry Coffi Herve Yao
发明人： Gregory James Scott , Mark Michael Nelson , Thierry Coffi Herve Yao
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11531 , H01L27/11521 , H01L27/11526 , H01L29/66825 , H01L29/7881
摘要： An electronic device includes a first memory cell and a second memory cell, of a nonvolatile memory array. The first memory cell includes a body region, a gate structure, a source region, and a drain region. The second memory cell includes a body region, a gate structure, a source region, and a drain region. In one embodiment, the body of the second memory cell is physically isolated from the body region of the first memory cell. A bitline segment is electrically connected to the drain region of the first memory cell and to the drain region of the second memory cell.
摘要翻译：电子设备包括非易失性存储器阵列的第一存储单元和第二存储单元。第一存储单元包括主体区域，栅极结构，源极区域和漏极区域。第二存储单元包括主体区域，栅极结构，源极区域和漏极区域。在一个实施例中，第二存储器单元的主体与第一存储单元的主体区域物理隔离。位线段电连接到第一存储单元的漏极区域和第二存储单元的漏极区域。

5. 发明授权

US06794691B2 Use of irregularly shaped conductive filler features to improve planarization of the conductive layer while reducing parasitic capacitance introduced by the filler features 失效
标题翻译：使用不规则形状的导电填料特征来改善导电层的平坦化，同时减少由填料特征引入的寄生电容
公开(公告)号：US06794691B2
公开(公告)日：2004-09-21
申请号：US10348093
申请日：2003-01-21
申请人： Mark Michael Nelson
发明人： Mark Michael Nelson
IPC分类号： H01L2973
CPC分类号： H01L21/31053 , H01L23/528 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduced capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.
摘要翻译：一种制造的多层集成电路，其中使用不规则形状且适当间隔的导电填料特征实现适当的平坦化，其间隔开，使得导电填料特征与有源导电区域的电容耦合减小。导电填料特征的整体布局面积减小，从而减少电容耦合与上下有源导电。此外，特征的相对较小的边缘最接近相同导电层中的有源导电，从而进一步减小电容耦合。

6. 发明授权

US06271539B1 Electrical diagnostic technique for silicon plasma-etch induced damage characterization 失效
标题翻译：硅等离子蚀刻诱导损伤表征的电气诊断技术
公开(公告)号：US06271539B1
公开(公告)日：2001-08-07
申请号：US08950000
申请日：1997-10-14
申请人： Mark Michael Nelson , Subhash Madhukar Deshmukh
发明人： Mark Michael Nelson , Subhash Madhukar Deshmukh
IPC分类号： H01L2358
CPC分类号： H01L22/34 , H01L22/12
摘要： Characterization of plasma-induced damage in semiconductor manufacturing has long been considered unimportant because the damage had no discernable effect on circuit performance. With increasing transistor counts on an integrated circuit, the damage-induced parasitics are becoming increasingly important. Electrical characterization of such effects provides a far more sensitive method for determining the extent of damage and the effectiveness of efforts to repair the damage. A measurement of diode leakage current through a plasma-etch effect test diode which is formed completely within an active device region, removed from field oxide regions quantifies the extent of damage created by a plasma and the effectiveness of a repair technique that may be applied to the process.
摘要翻译：长期以来，半导体制造中的等离子体引起的损伤的表征被认为是不重要的，因为损伤对电路性能没有明显的影响。随着集成电路中晶体管数量的增加，损伤引起的寄生效应变得越来越重要。这种影响的电气特性提供了一种更加敏感的方法来确定损伤的程度和修复损坏的努力的有效性。通过等离子蚀刻效应测试二极管的二极管泄漏电流的测量，其完全在活性器件区域内形成，从场氧化物区域移除，量化了由等离子体产生的损伤程度以及修复技术的有效性，可用于的过程。

7. 发明授权

US5683925A Manufacturing method for ROM array with minimal band-to-band tunneling 失效
标题翻译：具有最小带到带隧道的ROM阵列的制造方法
公开(公告)号：US5683925A
公开(公告)日：1997-11-04
申请号：US665150
申请日：1996-06-13
申请人： Rustom F. Irani , Reza Kazerounian , Mark Michael Nelson
发明人： Rustom F. Irani , Reza Kazerounian , Mark Michael Nelson
IPC分类号： H01L21/8246
CPC分类号： H01L27/112 , Y10S148/116 , Y10S438/981
摘要： A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) etching the ROM oxide layer only from the periphery area as per a later-removed core protect mask, d) providing a gate oxide layer over the entirety of the ROM array, e) laying down polysilicon rows in the core area as per a polysilicon mask and f) implanting a ROM implant into selected areas of the core area, thereby to produce turned off core transistors. The thickness of the gate oxide layer and the ROM oxide layer are independent of each other.
摘要翻译：描述了一种制造ROM阵列以最小化频带隧穿的方法。该方法包括以下步骤：a）根据稍后去除的位线掩模将位线注入衬底的芯区域，b）在整个衬底上提供ROM氧化层，c）蚀刻ROM氧化物层 d）在ROM阵列整体上提供栅极氧化层，e）根据多晶硅掩模放置芯区域中的多晶硅行，以及f）植入一个 ROM注入核心区域的选定区域，从而产生截止的核心晶体管。栅极氧化物层和ROM氧化物层的厚度彼此独立。

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