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1. 发明授权

US09438861B2 Integrating continuous and sparse streaming data 有权
标题翻译：集成连续和稀疏的流数据
公开(公告)号：US09438861B2
公开(公告)日：2016-09-06
申请号：US12612685
申请日：2009-11-05
申请人： John A. Bocharov , Geqiang (Sam) Zhang , Krishna Prakash Duggaraju , Lin Liu , Anirban Roy , Jack E. Freelander , Vishal Sood
发明人： John A. Bocharov , Geqiang (Sam) Zhang , Krishna Prakash Duggaraju , Lin Liu , Anirban Roy , Jack E. Freelander , Vishal Sood
IPC分类号： H04N7/173 , H04N21/4722 , H04N21/845 , H04N21/858
CPC分类号： H04N21/858 , H04N7/17318 , H04N21/2183 , H04N21/2187 , H04N21/23418 , H04N21/44016 , H04N21/4722 , H04N21/8456
摘要： A sparse streaming system provides a first-class means for sparse metadata to be added to streaming media presentations and to be delivered using an integrated data channel that is cacheable using readily available HTTP-based Internet caching infrastructure for increased scalability. The sparse streaming system stores a reference to a sparse track within a continuous track. If a continuous fragment arrives at the client that refers to a sparse fragment that the client has not yet retrieved, then the client requests the sparse fragment. In addition, each sparse fragment may include a backwards reference to the sparse fragment created immediately prior. The references in the continuous fragments make the client aware of new sparse track fragments, and the backwards references in the sparse track fragments ensure that the client has not missed any intervening sparse track fragments.
摘要翻译：稀疏流系统为稀疏元数据提供了一流的手段，可将其添加到流媒体演示文稿中，并使用可使用易于使用的基于HTTP的Internet缓存基础架构进行高速缓存的集成数据通道进行传送，以提高可扩展性。稀疏流系统存储对连续轨道内的稀疏轨迹的引用。如果连续片段到达客户端，引用客户端尚未检索的稀疏片段，则客户端请求稀疏片段。此外，每个稀疏片段可以包括对紧接在之前创建的稀疏片段的向后引用。连续片段中的引用使得客户端了解新的稀疏轨道片段，并且稀疏轨道片段中的向后引用确保客户端没有错过任何中间的稀疏轨道片段。

2. 发明授权

US09401217B2 Flash memory with improved read performance 有权
标题翻译：具有改进的读取性能的闪存
公开(公告)号：US09401217B2
公开(公告)日：2016-07-26
申请号：US14470359
申请日：2014-08-27
申请人： Anirban Roy , Jon S. Choy
发明人： Anirban Roy , Jon S. Choy
IPC分类号： G11C16/26 , G11C29/02 , G11C16/30 , G11C16/34
CPC分类号： G11C16/26 , G11C16/30 , G11C16/3445 , G11C16/3459 , G11C16/349 , G11C29/021 , G11C29/028 , G11C2216/04
摘要： A non-volatile memory device includes an array of memory cells and a plurality of word lines and voltage supply lines. Each memory cell of the array is coupled to one of the word lines. Each of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of a plurality of subsets of memory cells of the array. Each subset includes a plurality of memory cells. A voltage switch supplies a respective one of a plurality of aged voltages to each of the plurality of subsets of memory cells in the memory array on respective ones of the voltage supply lines. The aged voltage supplied to a first of the plurality of subsets of memory cells is different than the aged voltage supplied to a second of the plurality of subsets of memory cells.
摘要翻译：非易失性存储器件包括存储器单元阵列和多个字线和电压供应线。阵列的每个存储单元耦合到一行字线。多个电压供给线中的每一个耦合到该阵列的多个存储器单元的子集的存储单元子集的第一电压供应端。每个子集包括多个存储单元。电压开关将多个老化电压中的相应一个向存储器阵列中的各个电压供应线上的多个存储单元子集中的每一个提供。提供给存储器单元的多个子集中的第一个的老化电压与提供给多个存储单元子集中的第二子集的老化电压不同。

3. 发明授权

US09117754B2 Methods for extending floating gates for NVM cells to form sub-lithographic features and related NVM cells 有权
标题翻译：扩展NVM单元浮动栅格以形成亚光刻特征和相关NVM单元的方法
公开(公告)号：US09117754B2
公开(公告)日：2015-08-25
申请号：US14168093
申请日：2014-01-30
申请人： Anirban Roy , Craig A. Cavins
发明人： Anirban Roy , Craig A. Cavins
IPC分类号： H01L27/115 , H01L21/28 , H01L29/49 , H01L29/423 , H01L29/66 , H01L27/112
CPC分类号： H01L21/28273 , H01L27/112 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11548 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/42336 , H01L29/4916 , H01L29/66825 , H01L29/7881
摘要： Methods are disclosed for extending floating gate regions within floating gate cells to form sub-lithographic features. Related floating gate cells and non-volatile memory (NVM) systems are also disclosed. In part, the disclosed embodiments utilize a spacer etch to form extended floating gate regions and floating gate slits with sub-lithographic dimensions thereby achieving desired increased spacing between control gate layers and doped regions underlying floating gate structures while still allowing for reductions in the overall size of floating-gate NVM cells. These advantageous results are achieved in part by depositing an additional floating gate layer over previously formed floating gate regions and then using the spacer etch to form the extended floating gate regions as sidewall structures and sub-lithographic floating gate slits. The resulting floating gate structures reduce breakdown down risks, thereby improving device reliability.
摘要翻译：公开了用于在浮动栅极单元内扩展浮动栅极区域以形成亚光刻特征的方法。还公开了相关浮动栅极单元和非易失性存储器（NVM）系统。部分地，所公开的实施例利用间隔物蚀刻来形成具有亚光刻尺寸的扩展浮栅区域和浮置栅极狭缝，从而实现控制栅极层与浮栅结构之下的掺杂区域之间期望的增加的间隔，同时仍允许减小总体尺寸的浮栅NVM单元。这些有利的结果部分地通过在先前形成的浮动栅极区域上沉积额外的浮动栅极层，然后使用间隔物蚀刻来形成扩展的浮动栅极区域作为侧壁结构和亚光刻浮栅狭缝来实现。由此产生的浮动门结构降低了风险，从而提高了器件的可靠性。

4. 发明授权

US08657746B2 Glucose sensor signal purity analysis 有权
标题翻译：葡萄糖传感器信号纯度分析
公开(公告)号：US08657746B2
公开(公告)日：2014-02-25
申请号：US12914963
申请日：2010-10-28
申请人： Anirban Roy
发明人： Anirban Roy
IPC分类号： A61B5/05
CPC分类号： A61B5/7221 , A61B5/14532 , A61B5/14865 , A61B5/4839 , A61B5/6849 , A61B5/7203 , A61M5/1723 , G01N33/48
摘要： Disclosed are methods, apparatuses, etc. for glucose sensor signal purity analysis. In certain example embodiments, a series of samples of at least one sensor signal that is responsive to a blood glucose level of a patient may be obtained. Based at least partly on the series of samples, at least one metric may be determined to characterize one or more non-physiological anomalies of a representation of the blood glucose level of the patient by the at least one sensor signal. A reliability of the at least one sensor signal to represent the blood glucose level of the patient may be assessed based at least partly on the at least one metric. Other example embodiments are disclosed herein.
摘要翻译：公开了葡萄糖传感器信号纯度分析的方法，装置等。在某些示例性实施例中，可以获得响应于患者的血糖水平的至少一个传感器信号的一系列样本。至少部分地基于所述一系列样本，可以确定至少一个度量来表征由所述至少一个传感器信号表示所述患者的血糖水平的一个或多个非生理异常。可以至少部分地基于至少一个度量来评估用于表示患者的血糖水平的至少一个传感器信号的可靠性。本文公开了其它示例性实施例。

5. 发明申请

US20110313390A1 METHOD AND/OR SYSTEM FOR CLOSED-LOOP CONTROL OF GLUCOSE TO A TREATMENT RANGE 审中-公开
标题翻译：用于闭环控制葡萄糖至治疗范围的方法和/或系统
公开(公告)号：US20110313390A1
公开(公告)日：2011-12-22
申请号：US12820944
申请日：2010-06-22
申请人： Anirban Roy , Cesar C. Palerm
发明人： Anirban Roy , Cesar C. Palerm
IPC分类号： A61M5/00
摘要： Subject matter disclosed herein relates to monitoring and/or controlling blood glucose levels in patients. In particular, one or more substances may be delivered to a patient at a particular infusion rate while the patient's estimated glucose level is within a predetermined range. A different insulin infusion rate may then be applied if the patient's estimated blood glucose level deviates outside of the predetermined range.
摘要翻译：本文公开的主题涉及监测和/或控制患者血糖水平。特别地，当患者的估计葡萄糖水平在预定范围内时，一种或多种物质可以以特定的输注速率递送给患者。如果患者的估计血糖水平偏离预定范围，则可以应用不同的胰岛素输注速率。

6. 发明申请

US20110237917A1 CALIBRATION OF GLUCOSE MONITORING SENSOR AND/OR INSULIN DELIVERY SYSTEM 有权
标题翻译：葡萄糖监测传感器和/或胰岛素输送系统的校准
公开(公告)号：US20110237917A1
公开(公告)日：2011-09-29
申请号：US12748341
申请日：2010-03-26
申请人： Anirban Roy , Barry Keenan , Michael Kremliovsky
发明人： Anirban Roy , Barry Keenan , Michael Kremliovsky
IPC分类号： A61B5/145 , G06F19/00 , G01N33/48
CPC分类号： A61B5/1495 , A61B5/1451 , A61B5/14532 , A61B5/14865 , A61B5/4839 , A61B5/6849 , A61B5/7203 , A61B5/7221 , A61B5/725 , A61B5/7275 , A61B2560/0223 , A61M5/1723 , A61M2005/1726
摘要： Disclosed are methods, apparatuses, etc. for calibrating glucose monitoring sensors and/or insulin delivery systems. In certain example embodiments, blood glucose reference samples may be correlated with sensor measurements with regard to a delay associated with the sensor measurements. In certain other example embodiments, one or more parameters of a probability model may be estimated based on blood glucose reference sample-sensor measurement pairs. Based on such information, function(s) for estimating a blood-glucose concentration in a patient may be determined.
摘要翻译：公开了用于校准葡萄糖监测传感器和/或胰岛素递送系统的方法，装置等。在某些示例性实施例中，血糖参考样本可以与关于与传感器测量相关联的延迟的传感器测量值相关。在某些其他示例实施例中，可以基于血糖参考样本 - 传感器测量对来估计概率模型的一个或多个参数。基于这样的信息，可以确定用于估计患者血糖浓度的功能。

7. 发明申请

US20070127384A1 System to dynamically detect and correct errors in a session 有权
标题翻译：系统动态检测和纠正会话中的错误
公开(公告)号：US20070127384A1
公开(公告)日：2007-06-07
申请号：US11297205
申请日：2005-12-07
申请人： Sunil Chandrupatla , Nachiket Deshpande , Saikrishnan Gopalakrishnan , Anirban Roy
发明人： Sunil Chandrupatla , Nachiket Deshpande , Saikrishnan Gopalakrishnan , Anirban Roy
IPC分类号： H04J3/14
CPC分类号： H04L41/0663 , H04L67/14 , H04L67/145 , H04L69/40
摘要： A system for detecting and correcting an error in session between a client and a host over a network. When the system receives an indication of an error in a session, the system determines an error correction modification to the configuration of the session to correct the error. The system then implements the error correction modification to the configuration of the session and continues the session.
摘要翻译：一种用于通过网络检测和校正客户端和主机之间的会话中的错误的系统。当系统接收会话中的错误的指示时，系统确定对会话的配置的纠错修改以校正错误。然后系统对会话的配置实施纠错修改，并继续会话。

8. 发明授权

US09697897B2 Memory device with combined non-volatile memory (NVM) and volatile memory 有权
公开(公告)号：US09697897B2
公开(公告)日：2017-07-04
申请号：US14331274
申请日：2014-07-15
申请人： Michael A Sadd , Anirban Roy
发明人： Michael A Sadd , Anirban Roy
IPC分类号： G11C14/00
CPC分类号： G11C14/0063
摘要： A memory device includes a volatile memory cell, a non-volatile memory cell, and a transfer system connected between the volatile memory cell and the non-volatile memory cell. The transfer circuit allows data transfer from the volatile memory cell to the non-volatile memory cell when the memory device is operating in a first mode, and from the non-volatile memory cell to the volatile memory cell when the memory device is operating in a second mode.

9. 发明申请

US20160019964A1 MEMORY DEVICE WITH COMBINED NON-VOLATILE MEMORY (NVM) AND VOLATILE MEMORY 有权
标题翻译：具有组合非易失性存储器（NVM）和易失性存储器的存储器件
公开(公告)号：US20160019964A1
公开(公告)日：2016-01-21
申请号：US14331274
申请日：2014-07-15
申请人： MICHAEL A. SADD , ANIRBAN ROY
发明人： MICHAEL A. SADD , ANIRBAN ROY
IPC分类号： G11C14/00
CPC分类号： G11C14/0063
摘要： A memory device includes a volatile memory cell, a non-volatile memory cell, and a transfer system connected between the volatile memory cell and the non-volatile memory cell. The transfer circuit allows data transfer from the volatile memory cell to the non-volatile memory cell when the memory device is operating in a first mode, and from the non-volatile memory cell to the volatile memory cell when the memory device is operating in a second mode.
摘要翻译：存储器件包括易失性存储器单元，非易失性存储器单元和连接在易失性存储器单元和非易失性存储器单元之间的传输系统。当存储器设备在第一模式下操作时，传送电路允许从易失性存储器单元到非易失性存储器单元的数据传输，并且当存储器设备工作在第一模式时，从非易失性存储器单元到易失性存储器单元第二模式。

10. 发明申请

US20150093863A1 METHOD OF MAKING A FLOATING GATE NON-VOLATILE MEMORY (NVM) WITH BREAKDOWN PREVENTION 审中-公开
标题翻译：制造具有突破性预防的浮动门非易失性存储器（NVM）的方法
公开(公告)号：US20150093863A1
公开(公告)日：2015-04-02
申请号：US14041449
申请日：2013-09-30
申请人： ANIRBAN ROY
发明人： ANIRBAN ROY
IPC分类号： H01L21/28 , H01L27/115
CPC分类号： H01L29/40114 , H01L27/11521 , H01L29/66825
摘要： A method of making a semiconductor structure includes patterning a polysilicon layer on a substrate to form a first floating gate over a first active region in the substrate and a second floating gate over a second active region in the substrate. An opening between the first and second floating gates is filled with a dielectric material. The dielectric material is etched back so that a height of a remaining portion of the dielectric material is less than a height of the first and second floating gates. A second polysilicon layer is deposited over the first and second floating gates and the remaining portion of the dielectric material to form a word line for the first and second floating gates.
摘要翻译：制造半导体结构的方法包括在衬底上图案化多晶硅层，以在衬底中的第一有源区上方形成第一浮栅，并在衬底中的第二有源区上形成第二浮栅。在第一和第二浮栅之间的开口填充有电介质材料。电介质材料被回蚀刻，使得电介质材料的剩余部分的高度小于第一和第二浮栅的高度。第二多晶硅层沉积在第一和第二浮动栅极和电介质材料的剩余部分上，以形成用于第一和第二浮动栅极的字线。

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