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1. 发明授权

US08110476B2 Memory cell that includes a carbon-based memory element and methods of forming the same 有权
标题翻译：包含碳基记忆元件的记忆单元及其形成方法
公开(公告)号：US08110476B2
公开(公告)日：2012-02-07
申请号：US12418855
申请日：2009-04-06
申请人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Shricker
发明人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Shricker
IPC分类号： H01L21/00 , H01L21/06 , H01L29/02 , G11C11/00
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/0002 , G11C13/0009 , G11C13/025 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/285 , H01L51/0048 , Y10S977/712 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/734 , Y10S977/788 , Y10S977/789 , Y10S977/79 , Y10S977/855 , Y10S977/943
摘要： In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.
摘要翻译：根据本发明的方面，提供了一种形成存储单元的方法，所述方法包括在基板上形成操舵元件，以及形成耦合到所述操舵元件的存储元件，其中所述存储元件包括碳基材料具有不超过10个原子层的厚度。可以通过重复进行以下步骤来形成记忆元件：形成碳基材料层，该层具有约一个单层的厚度，并使碳基材料层进行热退火。还描述了其他方面。

2. 发明授权

US08659028B2 Three-dimensional memory device incorporating segmented array line memory array 有权
公开(公告)号：US08659028B2
公开(公告)日：2014-02-25
申请号：US11764789
申请日：2007-06-18
申请人： Roy E. Scheuerlein , Alper Ilkbahar , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： H01L27/10
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

3. 发明授权

US07433233B2 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法
公开(公告)号：US07433233B2
公开(公告)日：2008-10-07
申请号：US11764793
申请日：2007-06-18
申请人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
发明人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11568 , H01L27/1159
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

4. 发明授权

US08536015B2 Memory cell that includes a carbon-based memory element and methods of forming the same 有权
标题翻译：包含碳基记忆元件的记忆单元及其形成方法
公开(公告)号：US08536015B2
公开(公告)日：2013-09-17
申请号：US13351468
申请日：2012-01-17
申请人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
发明人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
IPC分类号： H01L21/00 , H01L21/06 , H01L29/02 , G11C11/00
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/0002 , G11C13/0009 , G11C13/025 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/285 , H01L51/0048 , Y10S977/712 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/734 , Y10S977/788 , Y10S977/789 , Y10S977/79 , Y10S977/855 , Y10S977/943
摘要： In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.
摘要翻译：根据本发明的方面，提供了形成金属 - 绝缘体 - 金属叠层的方法。该方法包括形成第一导电层，在第一导电层上形成电阻率切换碳基材料，并在碳基材料上形成第二导电层，其中碳基材料的厚度不大于十个原子层。还描述了其他方面。

5. 发明申请

US20100006812A1 CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：基于碳的电阻率切换材料及其形成方法
公开(公告)号：US20100006812A1
公开(公告)日：2010-01-14
申请号：US12499467
申请日：2009-07-08
申请人： Huiwen Xu , Xiying Chen , Roy E. Scheuerlein , Er-Xuan Ping , Tanmay Kumar , Alper Ilkbahar
发明人： Huiwen Xu , Xiying Chen , Roy E. Scheuerlein , Er-Xuan Ping , Tanmay Kumar , Alper Ilkbahar
IPC分类号： H01L29/02 , H01L21/00
CPC分类号： B82Y10/00 , B82Y30/00 , C23C16/26 , G11C13/0014 , G11C13/025 , G11C2213/19 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/149 , H01L45/1616
摘要： Memory devices including a carbon-based resistivity-switchable material, and methods of forming such memory devices are provided, the methods including introducing a processing gas into a processing chamber, wherein the processing gas includes a hydrocarbon compound and a carrier gas, and generating a plasma of the processing gas to deposit a layer of the carbon-based switchable material on a substrate within the processing chamber. Numerous additional aspects are provided.
摘要翻译：提供了包括碳基电阻率可切换材料的存储器件以及形成这种存储器件的方法，所述方法包括将处理气体引入处理室，其中所述处理气体包括烃化合物和载气，并且产生处理气体的等离子体，以将一层碳基可切换材料沉积在处理室内的基板上。还提供了许多其他方面。

6. 发明授权

US07233522B2 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法
公开(公告)号：US07233522B2
公开(公告)日：2007-06-19
申请号：US10729831
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
发明人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11568 , H01L27/1159
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

7. 发明授权

US07383476B2 System architecture and method for three-dimensional memory 有权
标题翻译：三维内存的系统架构和方法
公开(公告)号：US07383476B2
公开(公告)日：2008-06-03
申请号：US10774758
申请日：2004-02-09
申请人： Matthew P. Crowley , Luca G. Fasoli , Alper Ilkbahar , Mark G. Johnson , Bendik Kleveland , Thomas H. Lee , Roy E. Scheuerlein
发明人： Matthew P. Crowley , Luca G. Fasoli , Alper Ilkbahar , Mark G. Johnson , Bendik Kleveland , Thomas H. Lee , Roy E. Scheuerlein
IPC分类号： G11C29/00 , G11C11/00
CPC分类号： G06F11/1008 , G11C7/22 , G11C17/00
摘要： In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.
摘要翻译：在一个实施例中，提供了包括单片三维一次写入存储器阵列和以下系统块中的至少两个的芯片级结构：错误检查和校正电路（ECC）; 包含子数组的棋盘存储器阵列; 写控制器电荷泵; Vread发生器; 振荡器带隙参考发生器; 和页面寄存器/故障存储器。在另一个实施例中，提供了包括单片三维一次写入存储器阵列ECC和智能写入的芯片级架构。单片三维一次写入存储器阵列包括第一导体，第一导体上方的第一存储单元，第一存储单元上方的第二导体和第二导体上方的第二存储单元，其中第二导体是唯一的第一和第二存储单元之间的导体。

8. 发明授权

US06996017B2 Redundant memory structure using bad bit pointers 有权
标题翻译：冗余内存结构使用坏位指针
公开(公告)号：US06996017B2
公开(公告)日：2006-02-07
申请号：US10961501
申请日：2004-10-08
申请人： Roy E. Scheuerlein , Mark G. Johnson , Derek J. Bosch , Alper Ilkbahar , J. James Tringali
发明人： Roy E. Scheuerlein , Mark G. Johnson , Derek J. Bosch , Alper Ilkbahar , J. James Tringali
IPC分类号： G11C7/00
CPC分类号： G11C29/76 , G11C7/1006 , G11C7/24 , G11C29/44 , G11C29/4401 , G11C29/78
摘要： The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：这里描述的优选实施例涉及使用坏比特指针的冗余存储器结构。在一个优选实施例中，将数据写入第一多个存储单元，并且在存储单元之一中写入数据时检测到错误。响应于检测到的错误，指针被写入第二多个存储单元中，该指针标识第一多个存储单元中的哪个存储单元包含该错误。在读操作期间，从第一多个存储单元读取数据，并从第二多个存储单元读取指针。从指针中，识别包含错误的存储单元，并纠正错误。提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

9. 发明授权

US06765813B2 Integrated systems using vertically-stacked three-dimensional memory cells 有权
标题翻译：使用垂直堆叠的三维存储单元的集成系统
公开(公告)号：US06765813B2
公开(公告)日：2004-07-20
申请号：US10185588
申请日：2002-06-27
申请人： Roy E. Scheuerlein , J. James Tringali , Colm P. Lysaght , Alper Ilkbahar , Christopher S. Moore , David R. Friedman
发明人： Roy E. Scheuerlein , J. James Tringali , Colm P. Lysaght , Alper Ilkbahar , Christopher S. Moore , David R. Friedman
IPC分类号： G11C502
CPC分类号： G11C5/025 , G11C5/063 , G11C2213/71
摘要： Support circuitry for a three-dimensional memory array is formed in a substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：用于三维存储器阵列的支持电路至少部分地在三维存储器阵列的下方形成在衬底中，并且在三维存储器阵列下的衬底中限定开放区域。在一个优选实施例中，至少部分地在三维存储器阵列下的开放区域中形成一个或多个存储器阵列，而在另一个优选实施例中，实现一个或多个功能的逻辑电路至少部分地形成在开放区域三维记忆阵列。在另一优选实施例中，一个或多个存储器阵列和逻辑电路至少部分地形成在三维存储器阵列下方的开放区域中。提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

10. 发明授权

US08637870B2 Three-dimensional memory device incorporating segmented array line memory array 有权
标题翻译：三维存储器件结合分段阵列线存储器阵列
公开(公告)号：US08637870B2
公开(公告)日：2014-01-28
申请号：US13348336
申请日：2012-01-11
申请人： Roy E. Scheuerlein , Alper Ilkbahar , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： H01L27/10
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。在某些EEPROM实施例中，该阵列包括多层分段位线，其中多层具有段连接开关，并且共享与全局位线层的垂直连接。这样的存储器阵列可以通过对于半选择的存储器单元的更少的写入干扰效应来实现，并且可以用要被擦除的小得多的单元块来实现。

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