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1. 发明申请

US20060267657A1 Parallel trimming method and apparatus for a voltage controlled delay loop 有权
公开(公告)号：US20060267657A1
公开(公告)日：2006-11-30
申请号：US11141703
申请日：2005-05-31
申请人： Ronald Freyman , Mohammad Mobin , Vladimir Sindalovsky , Lane Smith
发明人： Ronald Freyman , Mohammad Mobin , Vladimir Sindalovsky , Lane Smith
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H04L7/0337
摘要： A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.

2. 发明申请

US20060132206A1 Trimming method and apparatus for voltage controlled delay loop with central interpolator 有权
标题翻译：具有中央插补器的电压控制延迟环微调方法和装置
公开(公告)号：US20060132206A1
公开(公告)日：2006-06-22
申请号：US11020022
申请日：2004-12-22
申请人： Ronald Freyman , Mohammad Mobin , Vladimir Sindalovsky , Lane Smith
发明人： Ronald Freyman , Mohammad Mobin , Vladimir Sindalovsky , Lane Smith
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0818
摘要： Methods and apparatus are provided for trimming a desired delay element in a voltage controlled delay loop. The disclosed trimming process comprises the steps of obtaining a first phase signal of a reference clock; applying the first phase signal along a first path to the desired delay element and a common delay element connected in series to the desired delay element; applying the reference clock along a second path to a first delay element and the common delay element; measuring a delay difference between the first and second paths at an output of the common delay element; and adjusting a delay of the desired delay element based on the measured delay difference. The trimming method may be repeated for each delay element in a voltage controlled delay loop.
摘要翻译：提供了用于在电压控制的延迟环中修整期望的延迟元件的方法和装置。所公开的修剪过程包括获得参考时钟的第一相位信号的步骤; 将第一相位信号沿着第一路径施加到期望的延迟元件和与期望的延迟元件串联连接的公共延迟元件; 沿着第二路径将参考时钟施加到第一延迟元件和公共延迟元件; 测量所述公共延迟元件的输出处的所述第一和第二路径之间的延迟差; 以及基于所测量的延迟差来调整所述延迟元件的延迟。可以在电压控制的延迟环路中对每个延迟元件重复修整方法。

3. 发明申请

US20070253477A1 Method and apparatus for determining a position of an offset latch employed for decision-feedback equalization 有权
标题翻译：用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置
公开(公告)号：US20070253477A1
公开(公告)日：2007-11-01
申请号：US11414522
申请日：2006-04-28
申请人： Christopher Abel , Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith
发明人： Christopher Abel , Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith
IPC分类号： H03H7/30
CPC分类号： H04L25/062 , H04L25/03057
摘要： Methods and apparatus are provided for determining a position of an offset latch employed for decision-feedback equalization. The position of an offset latch is determined by obtaining a plurality of samples of a data eye associated with a signal, the data eye comprised of a plurality of trajectories for transitions out of a given binary state; determining an amplitude of at least two of the trajectories based on the samples; and determining a position of an offset latch based on the determined amplitudes. The initial position of the offset latch can be placed, for example, approximately in the middle of the determined amplitudes for at least two of the trajectories. The initial position of the offset latch can be optionally skewed by a predefined amount to improve the noise margin.
摘要翻译：提供了用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置。通过获得与信号相关联的数据眼睛的多个采样来确定偏移锁存器的位置，数据眼睛包括用于从给定二进制状态转换的多个轨迹; 基于样本确定至少两个轨迹的振幅; 以及基于所确定的振幅来确定偏移锁存器的位置。偏移锁存器的初始位置可以被放置在例如至少两个轨迹的确定幅度的大约中间。偏移锁存器的初始位置可以可选地倾斜预定义的量以改善噪声容限。

4. 发明申请

US20070052460A1 Statically controlled clock source generator for VCDL clock phase trimming 失效
公开(公告)号：US20070052460A1
公开(公告)日：2007-03-08
申请号：US11221316
申请日：2005-09-07
申请人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
发明人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H04L7/0337
摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

5. 发明申请

US20070014342A1 Pseudo asynchronous serializer deserializer (SERDES) testing 有权
标题翻译：伪异步串行器解串器（SERDES）测试
公开(公告)号：US20070014342A1
公开(公告)日：2007-01-18
申请号：US11181286
申请日：2005-07-14
申请人： Vladimir Sindalovsky , Lane Smith , Ronald Freyman , Max Olsen
发明人： Vladimir Sindalovsky , Lane Smith , Ronald Freyman , Max Olsen
IPC分类号： H04B17/00
CPC分类号： G01R31/31715
摘要： The various embodiments of the invention provide an apparatus, system and method of asynchronous testing a serializer and deserializer data communication apparatus (SERDES) for determining frequency and phase locking to pseudo asynchronous input data having a continual phase offset. An exemplary apparatus includes a data sampler adapted to sample input serial data and to provide output data; a controlled tap delay with a selected tap having a phase offset from the input serial data, in which the selected tap is selectively coupleable to the data sampler to provide pseudo asynchronous input serial data; a first variable delay control adapted to delay a reference frequency provided to the controlled tap delay in response to the pseudo asynchronous input serial data; and a second delay control adapted to adjust the plurality of taps in response to the pseudo asynchronous input serial data. In additional embodiments, the pseudo asynchronous input serial data is provided from an interpolated phase from at least two selected taps.
摘要翻译：本发明的各种实施例提供了用于确定频率和相位锁定到具有连续相位偏移的伪异步输入数据的串行器和解串器数据通信装置（SERDES）的异步测试的装置，系统和方法。示例性装置包括适于对输入串行数据进行采样并提供输出数据的数据采样器; 具有与输入串行数据相位偏移的所选抽头的受控抽头延迟，其中所选择的抽头选择性地耦合到数据采样器以提供伪异步输入串行数据; 第一可变延迟控制器，其适于响应于所述伪异步输入串行数据延迟提供给受控抽头延迟的参考频率; 以及适于响应于所述伪异步输入串行数据来调整所述多个抽头的第二延迟控制。在另外的实施例中，伪异步输入串行数据从来自至少两个选择的抽头的内插相位提供。

6. 发明申请

US20060114045A1 Voltage controlled delay loop with central interpolator 有权
标题翻译：具有中央插补器的电压控制延迟回路
公开(公告)号：US20060114045A1
公开(公告)日：2006-06-01
申请号：US10999889
申请日：2004-11-30
申请人： Ronald Freyman , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
发明人： Ronald Freyman , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises at least one delay element to generate at least two phases of a reference clock; a central interpolator for interpolating the at least two phases of the reference clock to generate an interpolated signal; and an input that injects the interpolated signal into a delay stage. The central interpolator provides a fine phase control. In addition, a coarse phase control can optionally be achieved by selectively injecting the interpolated signal into a given delay stage. A further voltage controlled delay loop is disclosed with coarse and fine phase control using a number of interpolators.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟回路包括至少一个延迟元件以产生参考时钟的至少两个相位; 中央内插器，用于内插参考时钟的至少两个相位以产生内插信号; 以及将内插信号注入延迟级的输入。中央插值器提供精细的相位控制。此外，可以通过选择性地将内插信号注入到给定的延迟级中来可选地实现粗略的相位控制。公开了使用多个内插器的粗略和精细相位控制的另一个电压控制延迟回路。

7. 发明申请

US20060133557A1 Phase interpolator having a phase jump 有权
标题翻译：相位内插器具有相位跳变
公开(公告)号：US20060133557A1
公开(公告)日：2006-06-22
申请号：US11020021
申请日：2004-12-22
申请人： Ronald Freyman , Vladimir Sindalovsky , Lane Smith
发明人： Ronald Freyman , Vladimir Sindalovsky , Lane Smith
IPC分类号： H04L7/04
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0337
摘要： A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal. In addition, according to the present invention, the roaming tap interpolator includes a delay unit that selectively delays one or more of the first signal and the second signal to generate an interpolation signal, the interpolation signal selectively having a first phase or a second phase.
摘要翻译：公开了一种基于漫游抽头内插器来产生相位控制数据的方法和装置。本发明认识到，漫游抽头内插器在每个内插区域的边界处具有固有的非线性和不连续性。公开了一种漫游抽头内插器，其在时间上偏移插值曲线，以避免插值曲线中的不需要的伪影。漫游抽头内插器通常包括多个延迟元件，其延迟第一信号以产生每个具有相关联的相位的多个内插区域; 多路复用器，用于选择一个或多个插值区域; 以及内插器，用于处理所选择的一个或多个内插区域以产生第二信号。此外，根据本发明，漫游抽头插值器包括延迟单元，其选择性地延迟第一信号和第二信号中的一个或多个以产生内插信号，该内插信号选择性地具有第一相位或第二相位。

8. 发明申请

US20060114039A1 Voltage controlled delay loop and method with injection point control 有权
标题翻译：电压控制延时回路和注入点控制方法
公开(公告)号：US20060114039A1
公开(公告)日：2006-06-01
申请号：US10999900
申请日：2004-11-30
申请人： Ronald Freyman , Vladimir Sindalovsky , Lane Smith
发明人： Ronald Freyman , Vladimir Sindalovsky , Lane Smith
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0814 , H03L7/087 , H04L7/0337
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟环包括多个延迟元件; 以及输入，其选择性地将参考时钟注入到所述多个延迟元件中的任一个中。多个延迟元件串联连接，例如循环。在一个示例性实现中，每个延迟元件具有相关联的多路复用器，其选择参考时钟之一和来自先前延迟元件的信号。

9. 发明申请

US20120230454A1 RECEIVER TRAINING WITH CYCLE SLIP DETECTION AND CORRECTION 有权
标题翻译：接收器训练与循环滑动检测和校正
公开(公告)号：US20120230454A1
公开(公告)日：2012-09-13
申请号：US13043908
申请日：2011-03-09
申请人： Mohammad Mobin , Mark Trafford , Ye Liu , Vladimir Sindalovsky , Amaresh Malipatil
发明人： Mohammad Mobin , Mark Trafford , Ye Liu , Vladimir Sindalovsky , Amaresh Malipatil
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H04L7/0083 , H04L2025/037
摘要： In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.
摘要翻译：在所描述的实施例中，收发器包括具有眼睛监视器和周期滑移监视器的时钟和数据恢复模块（CDR）。循环滑移检测器监测CDR锁定状态，其可以通过在采样和/或转换定时检测中检测到滑移。循环滑移检测器提供检查点以感测系统发散，允许恢复CDR锁的机制。另外，当CDR超出锁定时，自适应设置的各种参数（例如，均衡器参数）在系统发散期间可能是无效的。因此，这些参数可能被系统声明为无效，未被使用。

10. 发明申请

US20070189360A1 Method and apparatus for generation of asynchronous clock for spread spectrum transmission 有权
标题翻译：用于产生扩频传输的异步时钟的方法和装置
公开(公告)号：US20070189360A1
公开(公告)日：2007-08-16
申请号：US11353431
申请日：2006-02-14
申请人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , William Wilson , Craig Ziemer
发明人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , William Wilson , Craig Ziemer
IPC分类号： H03D3/24 , H03D1/00 , H03D3/18 , H04L27/06 , H04B1/00
CPC分类号： H04L27/0014 , H04B1/7075 , H04L2027/0036
摘要： A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.
摘要翻译：用于扩频率控制的电路使用第一内插器在第一信号和第二信号之间进行相位插值，并且基于第一控制信号产生第一输出信号。第二内插器用于在第三信号和第四信号之间进行相位插值，并且基于第二控制信号产生第二输出信号。多路复用器用于基于选择信号选择第一输出信号或第二输出信号作为扩频时钟（SSCLK）。跳跃内插器控制用于与SSCLK同步地产生基于第一类型的相位调整请求的第一控制信号，基于第二类型的相位调整请求的第二控制信号，以及选择信号在改变第一控制信号或第二控制信号之后允许内插器稳定时间之后，在第一输出信号和第二输出信号之间切换多路复用器。

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