专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070189360A1 Method and apparatus for generation of asynchronous clock for spread spectrum transmission 有权
标题翻译：用于产生扩频传输的异步时钟的方法和装置
公开(公告)号：US20070189360A1
公开(公告)日：2007-08-16
申请号：US11353431
申请日：2006-02-14
申请人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , William Wilson , Craig Ziemer
发明人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , William Wilson , Craig Ziemer
IPC分类号： H03D3/24 , H03D1/00 , H03D3/18 , H04L27/06 , H04B1/00
CPC分类号： H04L27/0014 , H04B1/7075 , H04L2027/0036
摘要： A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.
摘要翻译：用于扩频率控制的电路使用第一内插器在第一信号和第二信号之间进行相位插值，并且基于第一控制信号产生第一输出信号。第二内插器用于在第三信号和第四信号之间进行相位插值，并且基于第二控制信号产生第二输出信号。多路复用器用于基于选择信号选择第一输出信号或第二输出信号作为扩频时钟（SSCLK）。跳跃内插器控制用于与SSCLK同步地产生基于第一类型的相位调整请求的第一控制信号，基于第二类型的相位调整请求的第二控制信号，以及选择信号在改变第一控制信号或第二控制信号之后允许内插器稳定时间之后，在第一输出信号和第二输出信号之间切换多路复用器。

2. 发明申请

US20070052460A1 Statically controlled clock source generator for VCDL clock phase trimming 失效
公开(公告)号：US20070052460A1
公开(公告)日：2007-03-08
申请号：US11221316
申请日：2005-09-07
申请人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
发明人： Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith , Craig Ziemer
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H04L7/0337
摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

3. 发明申请

US20070253477A1 Method and apparatus for determining a position of an offset latch employed for decision-feedback equalization 有权
标题翻译：用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置
公开(公告)号：US20070253477A1
公开(公告)日：2007-11-01
申请号：US11414522
申请日：2006-04-28
申请人： Christopher Abel , Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith
发明人： Christopher Abel , Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith
IPC分类号： H03H7/30
CPC分类号： H04L25/062 , H04L25/03057
摘要： Methods and apparatus are provided for determining a position of an offset latch employed for decision-feedback equalization. The position of an offset latch is determined by obtaining a plurality of samples of a data eye associated with a signal, the data eye comprised of a plurality of trajectories for transitions out of a given binary state; determining an amplitude of at least two of the trajectories based on the samples; and determining a position of an offset latch based on the determined amplitudes. The initial position of the offset latch can be placed, for example, approximately in the middle of the determined amplitudes for at least two of the trajectories. The initial position of the offset latch can be optionally skewed by a predefined amount to improve the noise margin.
摘要翻译：提供了用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置。通过获得与信号相关联的数据眼睛的多个采样来确定偏移锁存器的位置，数据眼睛包括用于从给定二进制状态转换的多个轨迹; 基于样本确定至少两个轨迹的振幅; 以及基于所确定的振幅来确定偏移锁存器的位置。偏移锁存器的初始位置可以被放置在例如至少两个轨迹的确定幅度的大约中间。偏移锁存器的初始位置可以可选地倾斜预定义的量以改善噪声容限。

4. 发明申请

US20060222135A1 Methods and apparatus for digital linearization of an analog phase interpolator 有权
标题翻译：用于数字线性化模拟相位内插器的方法和装置
公开(公告)号：US20060222135A1
公开(公告)日：2006-10-05
申请号：US11095770
申请日：2005-03-31
申请人： Mohammad Mobin , Gregory Sheets , Lane Smith , Craig Ziemer
发明人： Mohammad Mobin , Gregory Sheets , Lane Smith , Craig Ziemer
IPC分类号： H04L7/00
CPC分类号： H03K5/13 , H03K2005/00052 , H04L7/00
摘要： Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.
摘要翻译：提供了用于模拟相位内插器的数字线性化的方法和装置。所需的相位值最多可映射到相应的M比特值，其中M大于N。相应的M比特值被施加到相位插值器，以获得2' SUP> N <期望相位值。还提供了线性化相位内插器，其考虑过程，电压，温度或老化（PVTA）变化。

5. 发明申请

US20060222123A1 Method and apparatus for monitoring a data eye in a clock and data recovery system 审中-公开
标题翻译：用于在时钟和数据恢复系统中监视数据眼的方法和装置
公开(公告)号：US20060222123A1
公开(公告)日：2006-10-05
申请号：US11095178
申请日：2005-03-31
申请人： Mohammad Mobin , Gregory Sheets , Lane Smith
发明人： Mohammad Mobin , Gregory Sheets , Lane Smith
IPC分类号： H04B1/10
CPC分类号： H04B17/309 , H04B17/23 , H04L7/0025
摘要： Methods and apparatus are provided for monitoring a data eye associated with a received signal. A plurality of samples of the received signal are obtained for each unit interval based on a clock recovered from the received signal, to obtain an estimate of the data eye. According to one aspect of the invention, the samples are obtained substantially simultaneous to a decoding of the received signal. The collected data eye samples can optionally be processed, for example, to collect statistics on the received signal or to determine a distribution of the received signal.
摘要翻译：提供了用于监视与接收信号相关联的数据眼的方法和装置。基于从接收信号恢复的时钟，针对每个单位间隔获得接收信号的多个样本，以获得数据眼睛的估计。根据本发明的一个方面，基本上与所接收信号的解码同时获得样本。收集的数据眼睛样本可以可选地被处理，例如，以收集关于接收到的信号的统计信息或确定接收信号的分布。

6. 发明申请

US20060171485A1 Serdes auto calibration and load balancing 有权
公开(公告)号：US20060171485A1
公开(公告)日：2006-08-03
申请号：US11046669
申请日：2005-01-31
申请人： Donald Laturell , Gregory Sheets , Lane Smith , Mohammad Mobin
发明人： Donald Laturell , Gregory Sheets , Lane Smith , Mohammad Mobin
IPC分类号： H04L25/03
CPC分类号： H04L1/205
摘要： The present invention is used to automatically calibrate a SERDES device by utilizing information provided in the eye diagram of the received signal. In particular, the invention mitigates the components of determininistic jitter, such as ISI and frequency distortion. To achieve this goal, the invention enables the receive side of the SERDES to evaluate the quality of the eye received using a cost function. The invention calculates the cost function associated with the received data and then uses this information to effect an auto calibration of the SERDES device.

7. 发明申请

US20070147555A1 Method and apparatus for adjusting receiver gain based on received signal envelope detection 失效
标题翻译：基于接收信号包络检测来调整接收机增益的方法和装置
公开(公告)号：US20070147555A1
公开(公告)日：2007-06-28
申请号：US11318953
申请日：2005-12-23
申请人： Mohammad Mobin , Gregory Sheets , Lane Smith
发明人： Mohammad Mobin , Gregory Sheets , Lane Smith
IPC分类号： H04L27/08
CPC分类号： H04L25/063 , H03G3/30 , H03G3/3036 , H03G3/3052
摘要： Methods and apparatus are provided for adjusting receiver gain based on received signal envelope detection. The gain of a received signal is adjusted by obtaining a plurality of samples of the received signal for a given unit interval; determining an amplitude of the received signal based on the samples; and adjusting a receiver gain based on the determined amplitude. The received signal can be sampled, for example, using a plurality of latches. The value of the received signal can then be estimated by evaluating one or more of the latch values. Once the amplitude of the received signal is determined, one or more latches can be positioned at a desired target amplitude and the receiver gain can be adjusted until the amplitude of the received signal is within a desired tolerance of the specified target value.
摘要翻译：提供了基于接收信号包络检测来调整接收机增益的方法和装置。通过获得给定单位间隔的接收信号的多个样本来调整接收信号的增益; 基于样本确定接收信号的幅度; 以及基于所确定的幅度来调整接收机增益。可以例如使用多个锁存器对接收到的信号进行采样。然后可以通过评估一个或多个锁存值来估计接收信号的值。一旦确定了接收信号的幅度，就可以将一个或多个锁存器定位在期望的目标幅度，并且可以调整接收器增益，直到接收信号的振幅在指定目标值的期望公差内。

8. 发明申请

US20050078758A1 Method for training a transceiver for high speed communications 有权
标题翻译：用于训练用于高速通信的收发器的方法
公开(公告)号：US20050078758A1
公开(公告)日：2005-04-14
申请号：US10964056
申请日：2004-10-12
申请人： Pervez Aziz , Donald Laturell , Mohammad Mobin , Gregory Sheets , Lane Smith
发明人： Pervez Aziz , Donald Laturell , Mohammad Mobin , Gregory Sheets , Lane Smith
IPC分类号： G01R31/317 , H04B3/00 , H04B3/04 , H04L25/03
CPC分类号： G01R31/31715 , H04B3/04 , H04L25/03038 , H04L2025/03356 , H04L2025/03477 , H04L2025/03617
摘要： In training a SERDES, a Common Electrical Interface (CEI) training frame, having certain bits of information embedded therein, is transmitted over a path which comprises transmitter, channel, and receiver components. The present invention analyzes the resulting received signal and determines the effective aggregate channel impulse response of these three components. The invention then determines an estimate of the inverse of this aggregate channel and uses this determination to reduce distortions that have been introduced into a signal that has been transmitted over the path.
摘要翻译：在训练SERDES时，通过包含发射机，信道和接收机组件的路径发送具有嵌入其中的某些信息位的公共电接口（CEI）训练帧。本发明分析所得到的接收信号并确定这三个分量的有效总信道脉冲响应。然后，本发明确定该聚合信道的逆的估计，并且使用该确定来减少已经被引入到已经通过该路径传输的信号中的失真。

9. 发明申请

US20100219996A1 DC OFFSET DETECTION AND CORRECTION FOR USER TRAFFIC 有权
标题翻译： DC偏移检测和校正用户交通
公开(公告)号：US20100219996A1
公开(公告)日：2010-09-02
申请号：US12380639
申请日：2009-03-02
申请人： Christopher Abel , Mohammad Mobin , Robert Kapuschinsky , Lane Smith , Paul Tracy , Gregory Sheets
发明人： Christopher Abel , Mohammad Mobin , Robert Kapuschinsky , Lane Smith , Paul Tracy , Gregory Sheets
IPC分类号： H03M1/10
CPC分类号： H04L25/061
摘要： In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.
摘要翻译：在所描述的实施例中，采用例如时钟和数据恢复（CDR）的通信系统在输入数据流信号中检测并应用校正DC偏移，称为“DC偏移校准”。 DC偏移校准在输入电路（如输入放大器和检测锁存器）中对直流偏移进行静态校准，无输入数据，并在输入数据流运行期间对DC偏移进行统计校准，以校正直流电平的动态偏移。这种DC偏移校准使用用于检测DC偏移的输入数据流的数据眼睛测量，并施加相反的DC偏移以在实时业务期间维持相对平衡的数据眼睛。

10. 发明申请

US20070253517A1 Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权
标题翻译：用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量
公开(公告)号：US20070253517A1
公开(公告)日：2007-11-01
申请号：US11414521
申请日：2006-04-28
申请人： Pervez Aziz , Gregory Sheets , Vladimir Sindalovsky
发明人： Pervez Aziz , Gregory Sheets , Vladimir Sindalovsky
IPC分类号： H03D3/24
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译：提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式