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1. 发明申请

US20090235133A1 SLACK-BASED TRANSITION-FAULT TESTING 有权
标题翻译：基于SLACK的过渡故障测试
公开(公告)号：US20090235133A1
公开(公告)日：2009-09-17
申请号：US12469820
申请日：2009-05-21
申请人： Rohit Kapur , Tom W. Williams , Cyrus Hay
发明人： Rohit Kapur , Tom W. Williams , Cyrus Hay
IPC分类号： G01R31/28
CPC分类号： G01R31/31725
摘要： A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.
摘要翻译：一种生成用于检测集成电路（IC）中的过渡故障的测试模式的系统。在操作期间，系统为IC中的每个网络收到松弛时间。请注意，网络的松弛时间是给定网络在违反时序约束之前可以容忍的最小延迟时间。对于IC中的每个可能的过渡故障，系统使用IC中的网络的松弛时间来产生测试模式，该测试模式通过产生沿着最长路径传播到转换故障的转变来暴露过渡故障。

2. 发明授权

US07546500B2 Slack-based transition-fault testing 有权
标题翻译：基于松弛的过渡故障测试
公开(公告)号：US07546500B2
公开(公告)日：2009-06-09
申请号：US11366679
申请日：2006-03-02
申请人： Rohit Kapur , Tom W. Williams , Cyrus Hay
发明人： Rohit Kapur , Tom W. Williams , Cyrus Hay
IPC分类号： G01R31/28
CPC分类号： G01R31/31725
摘要： A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.
摘要翻译：一种生成用于检测集成电路（IC）中的过渡故障的测试模式的系统。在操作期间，系统为IC中的每个网络收到松弛时间。请注意，网络的松弛时间是给定网络在违反时序约束之前可以容忍的最小延迟时间。对于IC中的每个可能的过渡故障，系统使用IC中的网络的松弛时间来产生测试模式，该测试模式通过产生沿着最长路径传播到转换故障的转变来暴露过渡故障。

3. 发明授权

US07797601B2 Slack-based transition-fault testing 有权
标题翻译：基于松弛的过渡故障测试
公开(公告)号：US07797601B2
公开(公告)日：2010-09-14
申请号：US12469820
申请日：2009-05-21
申请人： Rohit Kapur , Tom W. Williams , Cyrus Hay
发明人： Rohit Kapur , Tom W. Williams , Cyrus Hay
IPC分类号： G01R31/28 , G01R31/30 , G01R31/26 , G11B20/20 , G06F9/45
CPC分类号： G01R31/31725
摘要： A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.
摘要翻译：一种生成用于检测集成电路（IC）中的过渡故障的测试模式的系统。在操作期间，系统为IC中的每个网络收到松弛时间。请注意，网络的松弛时间是给定网络在违反时序约束之前可以容忍的最小延迟时间。对于IC中的每个可能的过渡故障，系统使用IC中的网络的松弛时间来产生测试模式，该测试模式通过产生沿着最长路径传播到转换故障的转变来暴露过渡故障。

4. 发明申请

US20070206354A1 Slack-based transition-fault testing 有权
标题翻译：基于松弛的过渡故障测试
公开(公告)号：US20070206354A1
公开(公告)日：2007-09-06
申请号：US11366679
申请日：2006-03-02
申请人： Rohit Kapur , Tom Williams , Cyrus Hay
发明人： Rohit Kapur , Tom Williams , Cyrus Hay
IPC分类号： H05K7/20
CPC分类号： G01R31/31725
摘要： A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.
摘要翻译：一种生成用于检测集成电路（IC）中的过渡故障的测试模式的系统。在操作期间，系统为IC中的每个网络收到松弛时间。请注意，网络的松弛时间是给定网络在违反时序约束之前可以容忍的最小延迟时间。对于IC中的每个可能的过渡故障，系统使用IC中的网络的松弛时间来产生测试模式，该测试模式通过产生沿着最长路径传播到转换故障的转变来暴露过渡故障。

5. 发明授权

US08479067B2 Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry 有权
标题翻译：测试架构包括循环缓存链，选择性旁路扫描链段和阻塞电路
公开(公告)号：US08479067B2
公开(公告)日：2013-07-02
申请号：US12762048
申请日：2010-04-16
申请人： Anshuman Chandra , Jyotirmoy Saikia , Rohit Kapur
发明人： Anshuman Chandra , Jyotirmoy Saikia , Rohit Kapur
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318547
摘要： A test architecture adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values. The test architecture can include control logic for selecting between a linear mode and a cyclical mode. In the linear mode, only top level scan inputs are mapped to the scan chains. In the cyclical mode, outputs of the plurality of cyclical cache chains and top level scan inputs are mapped to the scan chains.
摘要翻译：测试架构通过为设计的扫描链提供的一组测试图案使用一个或多个循环高速缓存链来增加最小面积开销并增加编码带宽。与扫描链相关联的多路复用器可用于绕过包括未知值的扫描链段。阻塞电路可以编程为完全阻止一个或多个扫描链，包括未知值。测试架构可以包括用于在线性模式和循环模式之间进行选择的控制逻辑。在线性模式下，只有顶级扫描输入被映射到扫描链。在循环模式中，多个循环高速缓存链和顶层扫描输入的输出被映射到扫描链。

6. 发明申请

US20110040528A1 Systemic Diagnostics For Increasing Wafer Yield 有权
标题翻译：系统诊断用于提高晶圆产量
公开(公告)号：US20110040528A1
公开(公告)日：2011-02-17
申请号：US12854120
申请日：2010-08-10
申请人： Rohit Kapur , Mallika Kapur , Maya Kapur
发明人： Rohit Kapur , Mallika Kapur , Maya Kapur
IPC分类号： G06F15/00
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of performing systemic diagnostics for a wafer includes selecting a design for manufacturability (DFM) rule for analysis. For each IC chip on the wafer, two sets of IC features adjacent the rule can be extracted based on the chip's layout design. Upconverted diagnostics can be run to generate computed numbers associated with combination categories for each set. Zonal analysis can be run on the two sets using the computed numbers to derive metrics for the two sets. A report can be generated based on the zonal analysis.
摘要翻译：为晶片执行系统诊断的方法包括选择用于分析的可制造性（DFM）规则的设计。对于晶片上的每个IC芯片，可以基于芯片的布局设计提取与规则相邻的两组IC特征。可以运行上转换的诊断程序，以生成与每个组合的组合类别相关联的计算数字。可以使用计算的数字在两组上运行区域分析，以得出两组的度量。可以根据区域分析生成报告。

7. 发明授权

US07836368B2 Dynamically reconfigurable shared scan-in test architecture 有权
标题翻译：动态可重构共享扫描测试架构
公开(公告)号：US07836368B2
公开(公告)日：2010-11-16
申请号：US12546595
申请日：2009-08-24
申请人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
发明人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318536
摘要： A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
摘要翻译：提供了低开销动态可重配置的共享扫描测试架构。该测试架构有利地允许在每次移动的扫描操作期间改变扫描输入。重新配置扫描输入到每个移位周期扫描链映射的灵活性可以有利地减少测试数据量和测试应用时间。

8. 发明授权

US07836367B2 Dynamically reconfigurable shared scan-in test architecture 有权
公开(公告)号：US07836367B2
公开(公告)日：2010-11-16
申请号：US12539538
申请日：2009-08-11
申请人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
发明人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318536
摘要： A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

9. 发明授权

US07814444B2 Scan compression circuit and method of design therefor 有权
标题翻译：扫描压缩电路及其设计方法
公开(公告)号：US07814444B2
公开(公告)日：2010-10-12
申请号：US11807119
申请日：2007-05-25
申请人： Peter Wohl , John A. Waicukauski , Sanjay Ramnath , Rohit Kapur , Thomas W. Williams
发明人： Peter Wohl , John A. Waicukauski , Sanjay Ramnath , Rohit Kapur , Thomas W. Williams
IPC分类号： G06F17/50
CPC分类号： H03M7/30 , G06F17/505 , G06F2217/14
摘要： A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.
摘要翻译：基于扫描的电路包括通过多个观察逻辑实现的选择器。每个观察逻辑耦合到扫描链以接收要提供给组合式压缩机的数据。每个观察逻辑还耦合到组合压缩机的相应组输入线中的单个输入线，以选择性地从耦合的扫描链提供数据。每个观察逻辑可以耦合到相应组中的附加输入线（如果存在）。在（a）透明模式中，选择器可以在每个移位的基础上操作，其中数据被提供给所有输入线，并且（b）几个直接模式，其中来自仅一个扫描链的数据仅在每个压缩器输出处被提供而不重叠。

10. 发明申请

US20080301510A1 Dynamically Reconfigurable Shared Scan-In Test Architecture 有权
公开(公告)号：US20080301510A1
公开(公告)日：2008-12-04
申请号：US12178517
申请日：2008-07-23
申请人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic Neuveux , Suryanarayana Duggirala , Thomas W. Williams
发明人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic Neuveux , Suryanarayana Duggirala , Thomas W. Williams
IPC分类号： G06F11/00
CPC分类号： G01R31/318572 , G01R31/318536
摘要： A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

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