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1. 发明授权

US08464115B2 Fully X-tolerant, very high scan compression scan test systems and techniques 有权
标题翻译：全X容忍，非常高的扫描压缩扫描测试系统和技术
公开(公告)号：US08464115B2
公开(公告)日：2013-06-11
申请号：US13172752
申请日：2011-06-29
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318547
摘要： Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
摘要翻译：扫描测试和扫描压缩是实现成本降低和出货质量的关键。更复杂设计中的新缺陷类型需要增加压缩。然而，未知（X）值的增加的密度降低了有效压缩。扫描压缩方法可以为未知值的任何密度实现非常高的压缩和全覆盖。所描述的技术可以完全集成在测试设计（DFT）和自动测试模式生成（ATPG）流程中。在工业设计中使用这些技术的结果表明与其他方法相比是一致和可预测的优势。

2. 发明申请

US20080320348A1 Launch-On-Shift Support for On-Chip-Clocking 有权
标题翻译：片上时钟启动转移支持
公开(公告)号：US20080320348A1
公开(公告)日：2008-12-25
申请号：US11767606
申请日：2007-06-25
申请人： Timothy N. Ayres , Peter Wohl , John A. Waicukauski
发明人： Timothy N. Ayres , Peter Wohl , John A. Waicukauski
IPC分类号： G06F11/00
CPC分类号： G01R31/318552 , G01R31/318558 , G01R31/318594
摘要： A method to perform launch-on-shift scanning for integrated circuits having multiple clock domains is presented. An integrated circuit includes both capture clock domains and non-capture clock domains. The portions of the test vectors for non-capture clock domains are shifted into the scan chains of the non-capture clock domains and allowed to settle prior to the last shift launch cycle and the capture cycle of the capture clock domains. Thus, the ambiguity of the timing between the non-capture domains and the capture domains caused by asynchronous clock signals is eliminated.
摘要翻译：提出了一种用于对具有多个时钟域的集成电路执行启动扫描的方法。集成电路包括捕获时钟域和非捕获时钟域。非捕获时钟域的测试向量的部分被移入非捕获时钟域的扫描链，并允许在最后一个移位发射周期和捕获时钟域的捕获周期之前稳定。因此，消除了由异步时钟信号引起的非捕获域和捕获域之间的定时的不确定性。

3. 发明授权

US06959272B2 Method and system for generating an ATPG model of a memory from behavioral descriptions 有权
标题翻译：从行为描述生成记忆的ATPG模型的方法和系统
公开(公告)号：US06959272B2
公开(公告)日：2005-10-25
申请号：US09360069
申请日：1999-07-23
申请人： Peter Wohl , John Waicukauski , Timothy G. Hunkler
发明人： Peter Wohl , John Waicukauski , Timothy G. Hunkler
IPC分类号： G01R31/3181 , G01R31/3183 , G01R31/319 , G06F13/10 , G06F17/50
CPC分类号： G01R31/318357 , G01R31/31813 , G01R31/31919 , G06F17/5022
摘要： A method and system for constructing a structural model of a memory for use in ATPG (Automatic Test Pattern Generation). According to an embodiment of the present invention, behavioral models of memories of the simulation libraries are re-coded into simplified behavioral models using behavioral hardware description language (e.g., Verilog). Then, the simplified behavioral models are automatically converted into structural models that include ATPG memory primitives. The structural models are then stored for subsequent access during pattern generation. In one embodiment, for modeling random access memories (RAMs), the ATPG memory primitives include memory primitives, data bus primitives, address bus primitives, read-port primitives and macro output primitives. In another embodiment, for modeling content addressable memories (CAMs), the ATPG memory primitives include memory primitives, compare port primitives and macro output primitives. An advantage of the present invention is that functional equivalence between the simplified behavioral models and the simulation models can be easily verified with the same behavioral hardware description language simulator (e.g., Verilog simulator). Another advantage of the present invention is that very complicated memories, such as CAMs, can be accurately modeled for ATPG.
摘要翻译：一种用于构建用于ATPG（自动测试模式生成）的存储器的结构模型的方法和系统。根据本发明的实施例，使用行为硬件描述语言（例如，Verilog）将仿真库的存储器的行为模型重新编码成简化的行为模型。然后，简化的行为模型将自动转换为包含ATPG内存原语的结构模型。然后存储结构模型以便在模式生成期间进行后续访问。在一个实施例中，为了建模随机存取存储器（RAM），ATPG存储器原语包括存储器原语，数据总线原语，地址总线原语，读端口原语和宏输出原语。在另一个实施例中，为了建模内容可寻址存储器（CAM），ATPG存储器原语包括存储器原语，比较端口原语和宏输出原语。本发明的一个优点是可以用相同的行为硬件描述语言模拟器（例如，Verilog模拟器）容易地验证简化的行为模型和仿真模型之间的功能等同性。本发明的另一个优点是可以精确地为ATPG建模非常复杂的记忆，例如CAM。

4. 发明授权

US5796990A Hierarchical fault modeling system and method 失效
标题翻译：分层故障建模系统及方法
公开(公告)号：US5796990A
公开(公告)日：1998-08-18
申请号：US929578
申请日：1997-09-15
申请人： Mark Alan Erle , Matthew Christopher Graf , Peter Wohl
发明人： Mark Alan Erle , Matthew Christopher Graf , Peter Wohl
IPC分类号： G01R31/3183 , G06F11/263
CPC分类号： G01R31/318342
摘要： A system and method for generating a fault model for a logic circuit includes a data storage device for storing information relative to fault models or primitive elements in a logic circuit and for storing fault models for each level of design in a hierarchical logic circuit, a processor for processing the stored information relative to primitives and lower level fault models in the hierarchy for generating fault models for each succeeding higher level of design in the hierarchy, an input device for operator input of information to modify primitive fault models and a display subsystem for displaying various aspects of the hierarchical fault model generated in accordance with the present invention.
摘要翻译：用于产生逻辑电路的故障模型的系统和方法包括：数据存储装置，用于存储与逻辑电路中的故障模型或原始元件相关的信息，并用于存储分级逻辑电路中每个级别的设计的故障模型;处理器用于处理存储的相对于层级中的原语和下级故障模型的信息，用于为层级中的每个后续更高级别的设计生成故障模型，用于操作者输入信息以修改原始故障模型的输入设备和用于显示的显示子系统根据本发明生成的分层故障模型的各个方面。

5. 发明授权

US5668492A Integrated circuit clocking technique and circuit therefor 失效
标题翻译：集成电路时钟技术及其电路
公开(公告)号：US5668492A
公开(公告)日：1997-09-16
申请号：US617968
申请日：1996-03-13
申请人： Mark Eric Pedersen , Peter Wohl
发明人： Mark Eric Pedersen , Peter Wohl
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , H03K5/13 , H03K3/289
CPC分类号： G01R31/318552
摘要： A globally distributed system clock is received and selectively gated by local clock generators responsive to global control signals. The local clock generators, which are located proximately to sequential circuits having serial scan paths, produce scan and functional clock signals adapted to the sequential circuits, which may have a variety of required timing diagrams.
摘要翻译：全局分布式系统时钟被响应全局控制信号接收并由本地时钟发生器有选择地选通。位于具有串行扫描路径的顺序电路附近的本地时钟发生器产生适合于顺序电路的扫描和功能时钟信号，其可以具有各种所需的时序图。

6. 发明授权

US5508641A Integrated circuit chip and pass gate logic family therefor 失效
标题翻译：集成电路芯片和通门逻辑系列
公开(公告)号：US5508641A
公开(公告)日：1996-04-16
申请号：US359971
申请日：1994-12-20
申请人： David P. Appenzeller , Peter Wohl
发明人： David P. Appenzeller , Peter Wohl
IPC分类号： H03K19/0948 , H03K19/21
CPC分类号： H03K19/215 , H03K19/0948
摘要： An integrated circuit chip with high level logic functions formed from a pass gate logic family. The logic for each logic book includes at least one pass gate. Each book has complementary outputs and a pseudo latch attached to its outputs. If the book is of one FET type, the pseudo latch is of the opposite type. Books are placed in the logic function such that the output pseudo latches redrive opposite logic levels on alternating stages of series-connected books.
摘要翻译：具有高通逻辑功能的集成电路芯片，由通门逻辑系列组成。每个逻辑书的逻辑至少包括一个传递门。每本书都有互补输出和一个伪锁存器连接到其输出端。如果这本书是一种FET类型，则伪锁存器是相反的类型。书籍被放置在逻辑功能中，使得输出伪锁存器在串联连接的书籍的交替阶段上恢复相反的逻辑电平。

7. 发明申请

US20110258503A1 Fully X-tolerant, Very High Scan Compression Scan Test Systems And Techniques 有权
标题翻译：全X容忍，非常高的扫描压缩扫描测试系统和技术
公开(公告)号：US20110258503A1
公开(公告)日：2011-10-20
申请号：US13172752
申请日：2011-06-29
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/318547
摘要： Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
摘要翻译：扫描测试和扫描压缩是实现成本降低和出货质量的关键。更复杂设计中的新缺陷类型需要增加压缩。然而，未知（X）值的增加的密度降低了有效压缩。扫描压缩方法可以为未知值的任何密度实现非常高的压缩和全覆盖。所描述的技术可以完全集成在测试设计（DFT）和自动测试模式生成（ATPG）流程中。在工业设计中使用这些技术的结果表明与其他方法相比是一致和可预测的优势。

8. 发明申请

US20080256497A1 Scan compression circuit and method of design therefor 有权
标题翻译：扫描压缩电路及其设计方法
公开(公告)号：US20080256497A1
公开(公告)日：2008-10-16
申请号：US11807119
申请日：2007-05-25
申请人： Peter Wohl , John A. Waicukauski , Sanjay Ramnath , Rohit Kapur , Thomas W. Williams
发明人： Peter Wohl , John A. Waicukauski , Sanjay Ramnath , Rohit Kapur , Thomas W. Williams
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： H03M7/30 , G06F17/505 , G06F2217/14
摘要： A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.
摘要翻译：基于扫描的电路包括通过多个观察逻辑实现的选择器。每个观察逻辑耦合到扫描链以接收要提供给组合式压缩机的数据。每个观察逻辑还耦合到组合压缩机的相应组输入线中的单个输入线，以选择性地从耦合的扫描链提供数据。每个观察逻辑可以耦合到相应组中的附加输入线（如果存在）。在（a）透明模式中，选择器可以在每个移位的基础上操作，其中数据被提供给所有输入线，并且（b）几个直接模式，其中来自仅一个扫描链的数据仅在每个压缩器输出处被提供而不重叠。

9. 发明申请

US20080256274A1 Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit 有权
标题翻译：管道附加存储元件，用于移动组合扫描压缩电路的输入/输出数据
公开(公告)号：US20080256274A1
公开(公告)日：2008-10-16
申请号：US11786968
申请日：2007-04-13
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
IPC分类号： G06F13/38
CPC分类号： G01R31/318547
摘要： An electronic device includes a scan-based circuit that includes a combinational decompressor, a combinational compressor, scan chains, and logic which typically includes a number of storage elements. Cycle time normally needed to shift data into or out of a scan cell to/from an external interface of the electronic device is reduced by use of one or more additional storage element(s) located between the external interface and one of the combinational elements (decompressor/compressor). The one or more additional storage element(s) form a pipeline that shifts compressed data in stages, across small portions of an otherwise long path between the external interface and one of the combinational elements. Staged shifting causes the limit on cycle time to drop to the longest time required to traverse a stage of the pipeline. The reduced cycle time in turn enables a corresponding increase in shift frequency.
摘要翻译：电子设备包括基于扫描的电路，其包括组合式解压缩器，组合式压缩器，扫描链和通常包括多个存储元件的逻辑。通常需要通过使用位于外部接口和组合元件之一之间的一个或多个额外的存储元件来将数据移入或移出到电子设备的外部接口的扫描单元之外的周期时间（解压缩机/压缩机）。所述一个或多个附加存储元件形成流水线，其将压缩数据分阶段地跨越外部接口和组合元件之一之间的另外长的路径的小部分。分段移位导致循环时间的限制下降到穿越流水线所需的最长时间。缩短的周期时间又使移位频率相应增加。

10. 发明授权

US06385750B1 Method and system for controlling test data volume in deterministic test pattern generation 有权
标题翻译：用于在确定性测试模式生成中控制测试数据量的方法和系统
公开(公告)号：US06385750B1
公开(公告)日：2002-05-07
申请号：US09387865
申请日：1999-09-01
申请人： Rohit Kapur , Thomas W. Williams , John Waicukauski , Peter Wohl
发明人： Rohit Kapur , Thomas W. Williams , John Waicukauski , Peter Wohl
IPC分类号： G06F1100
CPC分类号： G01R31/31813
摘要： A method and system for improving the fault coverage of test vectors for testing integrated circuits. The present invention also provides a method and system for reducing the number of deterministic test vectors required for testing integrated circuits by inserting test points in a cost effective manner. According to an embodiment of the present invention, a fault list having all the potential faults of an integrated circuit design is initialized and all the potential faults are marked as untestable. A set of test patterns, T, for testing several of the potential faults are generated. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off untested faults. During fault simulation, fault propagation is monitored to determine the nets in the design to which faults were propagated. The nets at which fault propagation discontinues (e.g., de-sensitized) are also monitored. This information is collected over the set of test patterns, T. Based on the fault propagation information, test points are selectively inserted to maximize the fault coverage of the set of test patterns, T. In one embodiment, the nets to which most untested faults propagate are selected for test point insertion. The number of test points selected may be determined by user-defined parameters. These steps are then repeated for another set of set patterns until the desired fault coverage is achieved. By adding test points, the fault coverage of the test patterns is significantly improved, thus reducing the test data volume.
摘要翻译：一种改进测试矢量故障覆盖的方法和系统，用于测试集成电路。本发明还提供了一种通过以成本有效的方式插入测试点来减少测试集成电路所需的确定性测试向量的数量的方法和系统。根据本发明的实施例，初始化具有集成电路设计的所有潜在故障的故障列表，并将所有潜在故障标记为不可测。产生一组用于测试几个潜在故障的测试模式T。然后利用测试图案T对集成电路设计进行故障模拟处理，以标记未测试的故障。在故障模拟期间，监控故障传播，以确定传播故障的设计网络。还监测故障传播中断的网络（例如，去敏化）。该信息是通过一组测试模式T收集的。根据故障传播信息，选择性地插入测试点，以最大化测试模式集合T的故障覆盖。在一个实施例中，最未经测试的故障的网络选择传播以进行测试点插入。所选择的测试点的数量可以由用户定义的参数确定。然后对另一组设置模式重复这些步骤，直到实现所需的故障覆盖。通过添加测试点，测试模式的故障覆盖率显着提高，从而降低测试数据量。

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