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1. 发明授权

US07003751B1 Specification of the hierarchy, connectivity, and graphical representation of a circuit design 有权
标题翻译：电路设计的层次结构，连接性和图形表示的规范
公开(公告)号：US07003751B1
公开(公告)日：2006-02-21
申请号：US10340498
申请日：2003-01-10
申请人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
发明人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity attributes, and display attributes that describe a plurality of modules. The hierarchy attributes define parent-child relationships between modules, the connectivity attributes define input-output connections between modules, and the display attributes define a layout of the modules for viewing. Each of the objects has an associated method for generating a design specification in a selected format. When the program is executed, the design specification is generated from the set of objects. Depending on the capabilities of the available tools, the modules and logic elements are displayed in accordance with the display attributes either from the object-oriented program or from the design specification.
摘要翻译：用于创建电路设计的方法和装置。面向对象的程序实例化建模电路设计的多个对象。对象具有描述多个模块的层次属性，连接属性和显示属性。层次结构属性定义模块之间的父子关系，连接属性定义模块之间的输入输出连接，显示属性定义模块的布局以供查看。每个对象具有用于以所选格式生成设计规范的关联方法。当执行程序时，设计规范是从对象集合生成的。根据可用工具的功能，根据面向对象程序或设计规范的显示属性显示模块和逻辑元素。

2. 发明授权

US07203632B2 HDL co-simulation in a high-level modeling system 有权
标题翻译： HDL在高级建模系统中的共模拟
公开(公告)号：US07203632B2
公开(公告)日：2007-04-10
申请号：US10389161
申请日：2003-03-14
申请人： Roger B. Milne , L. James Hwang , Jeffrey D. Stroomer , Nabeel Shirazi , Haibing Ma , Jonathan B. Ballagh
发明人： Roger B. Milne , L. James Hwang , Jeffrey D. Stroomer , Nabeel Shirazi , Haibing Ma , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.
摘要翻译：用于模拟包括高级组件和HDL组件的电路设计操作的方法和装置。设计的高级组件在高级建模系统（HLMS）中进行模拟，并且使用HDL模拟器来模拟设计的HDL组件。将数据值从HLMS的数据类型转换为与HDL模拟器兼容的逻辑向量，以将每个数据值输入到HDL模拟器，并且将逻辑向量从HDL模拟器转换为数据类型的数据值与HDL模拟器的每个逻辑矢量输出的HLMS兼容。根据HLMS事件的时间和HDL组件的最大响应时间，事件被安排输入到HDL模拟器。

3. 发明授权

US07478030B1 Clock stabilization detection for hardware simulation 有权
标题翻译：硬件仿真的时钟稳定检测
公开(公告)号：US07478030B1
公开(公告)日：2009-01-13
申请号：US10600848
申请日：2003-06-19
申请人： Jonathan B. Ballagh , Roger B. Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Roger B. Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5027 , G06F2217/62
摘要： Method and apparatus for clock stabilization detection for hardware simulation is described. More particularly, a lock signal is obtained, for example from a digital clock module. A least common multiple (LCM) clock signal is generated, for example from a clock module. A control signal is generated at least partially responsive to the LCM clock signal and the lock signal. The control signal may be generated from a state machine and applied to select circuitry, where the control signal is used to mask application of the output clock signal responsive to the control signal.
摘要翻译：描述了用于硬件模拟的时钟稳定检测的方法和装置。更具体地，例如从数字时钟模块获得锁定信号。例如从时钟模块产生最小公共多（LCM）时钟信号。至少部分地响应于LCM时钟信号和锁定信号产生控制信号。控制信号可以从状态机产生并应用于选择电路，其中控制信号用于响应于控制信号屏蔽输出时钟信号的应用。

4. 发明授权

US07437280B1 Hardware-based co-simulation on a PLD having an embedded processor 有权
标题翻译：具有嵌入式处理器的PLD上的基于硬件的协同仿真
公开(公告)号：US07437280B1
公开(公告)日：2008-10-14
申请号：US11016378
申请日：2004-12-16
申请人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
发明人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Co-simulation of an electronic circuit design using an embedded processor on a programmable logic device (PLD). The programmable logic resources of a PLD are used to perform hardware-based co-simulation of a first portion of the electronic circuit design. Software-based co-simulation of a second portion of the electronic circuit design is performed using the embedded processor.
摘要翻译：使用可编程逻辑器件（PLD）上的嵌入式处理器进行电子电路设计的协同仿真。 PLD的可编程逻辑资源用于执行电子电路设计的第一部分的基于硬件的协同仿真。使用嵌入式处理器执行电子电路设计的第二部分的基于软件的协同仿真。

5. 发明授权

US07363600B1 Method of simulating bidirectional signals in a modeling system 有权
标题翻译：在建模系统中模拟双向信号的方法
公开(公告)号：US07363600B1
公开(公告)日：2008-04-22
申请号：US10691343
申请日：2003-10-21
申请人： Jonathan B. Ballagh , Roger B. Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Roger B. Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022
摘要： A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.
摘要翻译：在支持单向数据流的高级建模系统中对设计建模的方法可以包括识别总线块以表示系统中双向总线的连接性。总线块可以与总线串联表示。分接头可以通过总线接口连接总线。在仿真期间，总线模块仿真与分接口的输入线串联的三态缓冲器的行为。在合成期间，可以模拟总线端口到总线块的相反数据路由取向的单向输入和输出线对可以被折叠到单个总线端口。该合成可以进一步生成可以在抽头输入和总线之间设置三态缓冲器的网表。网表还可以表示用于驱动水龙头输出的三态缓冲器的布局。

6. 发明授权

US07194705B1 Simulation of integrated circuitry within a high-level modeling system using hardware description language circuit descriptions 有权
标题翻译：在使用硬件描述语言电路描述的高级建模系统中对集成电路进行仿真
公开(公告)号：US07194705B1
公开(公告)日：2007-03-20
申请号：US10388692
申请日：2003-03-14
申请人： Kumar Deepak , L. James Hwang , Singh Vinay Jitendra , Haibing Ma , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer , Jimmy Zhenming Wang
发明人： Kumar Deepak , L. James Hwang , Singh Vinay Jitendra , Haibing Ma , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer , Jimmy Zhenming Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.
摘要翻译：描述了使用电路的一个或多个电路描述语言表示来模拟建模系统内的集成电路的方法，装置和计算机可读介质。例如，电路的一个或多个电路描述语言表示的电路描述语言表示被转换成程序语言电路描述。执行第一模拟处理并从其获得输入数据。以输入数据作为参数输入来执行第二模拟处理以产生输出数据，第二模拟处理从程序语言电路描述导出。通过第二次模拟处理产生的输出数据被提供给第一个仿真过程。

7. 发明授权

US07934185B1 Method of simulating bidirectional signals in a modeling system 有权
标题翻译：在建模系统中模拟双向信号的方法
公开(公告)号：US07934185B1
公开(公告)日：2011-04-26
申请号：US12054247
申请日：2008-03-24
申请人： Jonathan B. Ballagh , Roger Brent Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Roger Brent Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.
摘要翻译：在支持单向数据流的高级建模系统中对设计建模的方法可以包括识别总线块以表示系统中双向总线的连接性。总线块可以与总线串联表示。分接头可以通过总线接口连接总线。在仿真期间，总线模块仿真与分接口的输入线串联的三态缓冲器的行为。在合成期间，可以模拟总线端口到总线块的相反数据路由取向的单向输入和输出线对可以被折叠到单个总线端口。该合成可以进一步生成可以在抽头输入和总线之间设置三态缓冲器的网表。网表还可以表示用于驱动水龙头输出的三态缓冲器的布局。

8. 发明授权

US07284225B1 Embedding a hardware object in an application system 有权
标题翻译：在应用系统中嵌入一个硬件对象
公开(公告)号：US07284225B1
公开(公告)日：2007-10-16
申请号：US10850133
申请日：2004-05-20
申请人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Nabeel Shirazi
发明人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Nabeel Shirazi
IPC分类号： G06F17/50 , G06F15/177 , G06F9/06 , G06F3/00 , G06F13/10 , G06F13/38
CPC分类号： G06F17/5054 , G06F2217/86
摘要： Various approaches for interfacing an application-independent hardware object with an application system are disclosed. The various approaches involve instantiating a first object that contains at least one configuration parameter. The configuration parameter specifies a location of a configuration bitstream for implementing functions of the hardware object in a programmable logic circuit. A second object is instantiated and is configured to open, in response to a program call to a first function provided by the second object, an interface to the programmable logic circuit. A programmable logic circuit is configured with the configuration bitstream in response to instantiation of the second object, and, in response to a program call to the first function, an interface to the programmable logic circuit is opened.
摘要翻译：公开了用于将应用无关硬件对象与应用系统连接的各种方法。各种方法涉及实例化包含至少一个配置参数的第一对象。配置参数指定用于在可编程逻辑电路中实现硬件对象的功能的配置比特流的位置。第二个对象被实例化并且被配置为响应于对由第二对象提供的第一功能的程序调用而打开到可编程逻辑电路的接口。可编程逻辑电路被配置为响应于第二对象的实例化而具有配置比特流，并且响应于对第一功能的程序调用，打开到可编程逻辑电路的接口。

9. 发明授权

US07739092B1 Fast hardware co-simulation reset using partial bitstreams 有权
标题翻译：使用部分比特流快速硬件协同仿真复位
公开(公告)号：US07739092B1
公开(公告)日：2010-06-15
申请号：US11343554
申请日：2006-01-31
申请人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Kevin Marc Neilson , Nabeel Shirazi
发明人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Kevin Marc Neilson , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5022
摘要： A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.
摘要翻译：复位用于硬件协同仿真的可编程逻辑器件（PLD）的方法可以包括将完整比特流加载到PLD中。完整的比特流可以用PLD来编程以用于第一次仿真的电路设计。该方法还可以包括将部分比特流加载到PLD中，从而重置不具有复位功能的电路设计的至少一个组件，使得电路设计被初始化以用于随后的模拟。

10. 发明授权

US07433813B1 Embedding a co-simulated hardware object in an event-driven simulator 有权
标题翻译：在事件驱动的模拟器中嵌入一个共同模拟的硬件对象
公开(公告)号：US07433813B1
公开(公告)日：2008-10-07
申请号：US10850178
申请日：2004-05-20
申请人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Nabeel Shirazi
发明人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Various approaches for embedding a hardware object in an event-driven simulator are disclosed. The various approaches involve generating an HDL proxy component having an HDL definition of each port of the hardware object and respective event handler functions associated with input ports of the HDL proxy component. The event handler functions are responsive to simulation events appearing on the input ports. A configuration bitstream is generated for implementing the hardware object on a programmable logic circuit, and a first object is generated to contain configuration parameter values indicating characteristics of the ports and a location of the configuration bitstream. A second object is generated and is configured to initiate configuration of the programmable logic circuit with the configuration bitstream. The second object further provides input data to and receives output data from the programmable logic circuit.
摘要翻译：公开了将硬件对象嵌入到事件驱动模拟器中的各种方法。各种方法涉及生成具有硬件对象的每个端口的HDL定义的HDL代理组件以及与HDL代理组件的输入端口相关联的相应事件处理程序功能。事件处理函数响应出现在输入端口上的模拟事件。生成用于在可编程逻辑电路上实现硬件对象的配置比特流，并且生成第一对象以包含指示端口的特性和配置比特流的位置的配置参数值。产生第二个目标，并且被配置为启动具有配置比特流的可编程逻辑电路的配置。第二个目的还提供输入数据并从可编程逻辑电路接收输出数据。

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