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    • 5. 发明授权
    • Structure and method to fabricate pFETS with superior GIDL by localizing workfunction
    • 通过定位功能来制造具有优异GIDL的pFETS的结构和方法
    • US08299530B2
    • 2012-10-30
    • US12717375
    • 2010-03-04
    • Chengwen PeiRoger A. Booth, Jr.Kangguo ChengJoseph ErvinRavi M. TodiGeng Wang
    • Chengwen PeiRoger A. Booth, Jr.Kangguo ChengJoseph ErvinRavi M. TodiGeng Wang
    • H01L27/12H01L21/8238
    • H01L21/22H01L21/8238H01L27/092
    • A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.
    • 提供了一种半导体结构及其形成方法,其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏,使得pFET的栅极/ SD(源极/漏极)重叠区域为 适应平带,但不影响设备通道区域的功能。 该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。 所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。 沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。 该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域,其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。 通过离子注入或退火可形成局部功能调谐区域。