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1. 发明申请

US20060048120A1 Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations 失效
公开(公告)号：US20060048120A1
公开(公告)日：2006-03-02
申请号：US10926595
申请日：2004-08-26
申请人： Rock Archambault , Robert Blainey , Yaoqing Gao , Allan Martin , James McInnes , Francis O'Connell
发明人： Rock Archambault , Robert Blainey , Yaoqing Gao , Allan Martin , James McInnes , Francis O'Connell
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.

2. 发明申请

US20050138613A1 Method and system for code modification based on cache structure 失效
标题翻译：基于缓存结构的代码修改方法和系统
公开(公告)号：US20050138613A1
公开(公告)日：2005-06-23
申请号：US10855729
申请日：2004-05-27
申请人： Roch Archambault , Robert Blainey , Yaoqing Gao , John McCalpin , Francis O'Connell , Pascal Vezolle , Steven White
发明人： Roch Archambault , Robert Blainey , Yaoqing Gao , John McCalpin , Francis O'Connell , Pascal Vezolle , Steven White
IPC分类号： G06F9/44 , G06F9/45 , G06F12/02
CPC分类号： G06F8/4442
摘要： A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining static and dynamic characteristics for the instructions; selecting a modification factor for the instructions based on a number of separate equivalent sections forming a cache in a processor which is processing the instructions; and modifying the instructions to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.
摘要翻译：提供了修改形成循环的指令的方法和系统。修改形成循环的指令的方法包括修改形成循环的指令，包括：确定指令的静态和动态特性; 基于在正在处理所述指令的处理器中形成高速缓存的单独的等效部分的数量来选择所述指令的修改因子; 以及当指令满足基于静态和动态特性的修改标准时，修改指令以根据修改因子和静态和动态特性来交织循环中的指令。

3. 发明申请

US20050246700A1 Compiler with cache utilization optimizations 失效
标题翻译：具有缓存利用率优化的编译器
公开(公告)号：US20050246700A1
公开(公告)日：2005-11-03
申请号：US10835756
申请日：2004-04-30
申请人： Roch Archambault , Robert Blainey , Yaoqing Gao
发明人： Roch Archambault , Robert Blainey , Yaoqing Gao
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A compiling program with cache utilization optimizations employs an inter-procedural global analysis of the data access patterns of compile units to be processed. The global analysis determines sufficient information to allow intelligent application of optimization techniques to be employed to enhance the operation and utilization of the available cache systems on target hardware.
摘要翻译：具有缓存利用率优化的编译程序采用对要处理的编译单元的数据访问模式的跨过程全局分析。全局分析确定足够的信息，以允许智能应用优化技术来增强目标硬件上可用的高速缓存系统的操作和利用。

4. 发明授权

US09038045B2 Unified parallel C work-sharing loop construct transformation 有权
标题翻译：统一并行C工作共享循环构造转换
公开(公告)号：US09038045B2
公开(公告)日：2015-05-19
申请号：US13296705
申请日：2011-11-15
申请人： Yaoqing Gao , Liangxiao Hu , Raul Esteban Silvera , Ettore Tiotto
发明人： Yaoqing Gao , Liangxiao Hu , Raul Esteban Silvera , Ettore Tiotto
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/51 , G06F8/314
摘要： Control flow information and data flow information associated with a program containing a upc_forall loop are built. A shared reference map data structure using the control flow information and the data flow information is created. All local shared accesses are hashed to facilitate a constant access stride after being rewritten. All local shared references in a hash entry having a longest list are privatized. The upc_forall loop is rewritten into a for loop. Responsive to a determination that an unprocessed upc_forall loop does not exist, dead store elimination is run. The control flow information and the data flow information associated with the program containing the for loop is rebuilt.
摘要翻译：构建与包含upc_forall循环的程序相关联的控制流信息和数据流信息。创建使用控制流信息和数据流信息的共享参考地图数据结构。所有本地共享访问都被散列，以便在重写后能够持续访问。具有最长列表的哈希条目中的所有本地共享引用被私有化。 upc_forall循环被重写为for循环。响应于确定未处理的upc_forall循环不存在，执行死区消除。与包含for循环的程序相关联的控制流信息和数据流信息被重建。

5. 发明授权

US08656142B2 Managing multiple speculative assist threads at differing cache levels 失效
标题翻译：管理不同缓存级别的多个投机辅助线程
公开(公告)号：US08656142B2
公开(公告)日：2014-02-18
申请号：US12903620
申请日：2010-10-13
申请人： Tong Chen , Yaoqing Gao
发明人： Tong Chen , Yaoqing Gao
IPC分类号： G06F9/30
CPC分类号： G06F12/0862
摘要： An illustrative embodiment provides a computer-implemented process for managing multiple speculative assist threads for data pre-fetching that sends a command from an assist thread of a first processor to second processor and a memory, wherein parameters of the command specify a processor identifier of the second processor, responsive to receiving the command, reply by the second processor indicating an ability to receive a cache line that is a target of a pre-fetch, responsive to receiving the command replying by the memory indicating a capability to provide the cache line, responsive to receiving replies from the second processor and the memory, sending, by the first processor, a combined response to the second processor and the memory, wherein the combined response indicates an action, and responsive to the action indicating a transaction can continue sending the requested cache line, by the memory, to the second processor into a target cache level on the second processor.
摘要翻译：示例性实施例提供了一种用于管理用于数据预取的多个推测辅助线程的计算机实现的过程，其将命令从第一处理器的辅助线程发送到第二处理器和存储器，其中该命令的参数指定处理器标识符第二处理器，响应于接收到所述命令，响应于接收到指示提供所述高速缓存行的能力的由所述存储器回复的命令，所述第二处理器的指示接收作为所述预取的目标的高速缓存行的能力，响应于从所述第二处理器和所述存储器接收到的答复，由所述第一处理器发送对所述第二处理器和所述存储器的组合响应，其中所述组合响应指示动作，并且响应于所述动作指示事务可以继续发送所述存储器将所请求的高速缓存行提供给所述第二处理器到所述第二处理器上的目标高速缓存级别。

6. 发明授权

US08490065B2 Method and apparatus for software-assisted data cache and prefetch control 有权
标题翻译：用于软件辅助数据缓存和预取控制的方法和装置
公开(公告)号：US08490065B2
公开(公告)日：2013-07-16
申请号：US11250054
申请日：2005-10-13
申请人： Roch Archambault , Yaoqing Gao , Francis Patrick O'Connell , Robert Brett Tremaine , Michael Edward Wazlowski , Steven Wayne White , Lixin Zhang
发明人： Roch Archambault , Yaoqing Gao , Francis Patrick O'Connell , Robert Brett Tremaine , Michael Edward Wazlowski , Steven Wayne White , Lixin Zhang
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F9/3879 , G06F8/4442 , G06F9/30047 , G06F9/3455 , G06F12/0862 , G06F2212/6028
摘要： The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.
摘要翻译：本发明提供了一种用于编译用于管理高速缓存系统的指令的计算机实现的方法，装置和计算机可用程序代码。分析循环结构以识别指令中的缓存和预取条件的数据使用特征以形成识别的预取条件。基于数据使用特性和识别的预取条件将一组控制指令插入到指令中以形成多个修改的指令。编译多组修改指令的集合以生成用于执行的代码以形成编译指令。编译指令中的一组控制指令形成高速缓存管理策略以在执行编译指令期间控制存储器系统中数据的移动。

7. 发明授权

US08458679B2 May-constant propagation 失效
标题翻译：可能恒定传播
公开(公告)号：US08458679B2
公开(公告)日：2013-06-04
申请号：US12888230
申请日：2010-09-22
申请人： Roch G. Archambault , Shimin Cui , Yaoqing Gao
发明人： Roch G. Archambault , Shimin Cui , Yaoqing Gao
IPC分类号： G06F9/45
CPC分类号： G06F8/43
摘要： May-constant propagation is a technique used to propagate a constant through the call graph and control flow graph by ignoring possible kills and re-definitions with low probability. Variables associated with constants in program code are determined. Execution flow probabilities are executed for code segments of the program code that comprise the variables. The execution flow probabilities are calculated based on flow data for the program code. At least a first of the code segments is determined to have a high execution flow probability. The first of the constants associated with the first variable are propagated through the flow data to generate modified flow data.
摘要翻译：可能常数传播是一种用于通过忽略可能的死亡和低概率重定义来通过调用图和控制流程图传播常量的技术。确定与程序代码中的常量相关联的变量。对包含变量的程序代码的代码段执行执行流概率。基于程序代码的流程数据计算执行流概率。至少第一代码段被确定为具有高的执行流概率。与第一个变量关联的第一个常量通过流数据传播，以产生修改的流数据。

8. 发明授权

US08191057B2 Systems, methods, and computer products for compiler support for aggressive safe load speculation 失效
标题翻译：用于编译器的系统，方法和计算机产品支持积极的安全负载推测
公开(公告)号：US08191057B2
公开(公告)日：2012-05-29
申请号：US11845491
申请日：2007-08-27
申请人： Roch G. Archambault , Geoffrey O. Blandy , Roland Froese , Yaoqing Gao , Liangxiao Hu , James L. McInnes , Raul E. Silvera
发明人： Roch G. Archambault , Geoffrey O. Blandy , Roland Froese , Yaoqing Gao , Liangxiao Hu , James L. McInnes , Raul E. Silvera
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/4441
摘要： Systems, methods and computer products for compiler support for aggressive safe load speculation. Exemplary embodiments include a method for aggressive safe load speculation for a compiler in a computer system, the method including building a control flow graph, identifying both countable and non-countable loops, gathering a set of candidate loops for load speculation, and for each candidate loop in the set of candidate loops gathered for load speculation, computing an estimate of the iteration count, delay cycles, and code size, performing a profitability analysis and determining an unroll factor based on the delay cycles and the code size, transforming the loop by generating a prologue loop to achieve data alignment and an unrolled main loop with loop directives, indicating which loads can safely be executed speculatively and performing low-level instruction scheduling on the generated unrolled main loop.
摘要翻译：用于编译器的系统，方法和计算机产品支持攻击性安全负载推测。示例性实施例包括用于计算机系统中的编译器的积极的安全负载推测的方法，所述方法包括构建控制流程图，识别可计数和不可计数循环，收集用于负载推测的一组候选循环，以及针对每个候选针对负载推测收集的候选循环集中的循环，计算迭代计数，延迟周期和代码大小的估计，执行盈利能力分析并基于延迟周期和代码大小确定展开因子，将循环转换为生成序言循环以实现数据对齐和循环指令的展开主循环，指示哪些负载可以安全地推测执行，并对生成的未展开主循环执行低级指令调度。

9. 发明授权

US08091079B2 Implementing shadow versioning to improve data dependence analysis for instruction scheduling 失效
标题翻译：实施影子版本化，提高指令调度的数据依赖性分析
公开(公告)号：US08091079B2
公开(公告)日：2012-01-03
申请号：US11846910
申请日：2007-08-29
申请人： Roch G. Archambault , Yaoqing Gao , Raul E. Silvera , Peng Zhao
发明人： Roch G. Archambault , Yaoqing Gao , Raul E. Silvera , Peng Zhao
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/443
摘要： A method for implementing shadow versioning to improve data dependence analysis for instruction scheduling in compiling code, and to identify loops within the code to be compiled, for each loop initializing a dependence a matrix, for each loop shadow identifying symbols that are accessed by the loop, examining dependencies, storing, comparing and classifying the dependence vectors, generating new shadow symbols, replacing the old shadow symbols with the new shadow symbols, generating alias relationships between the newly created shadow symbols, scheduling instructions and compiling the code.
摘要翻译：一种用于实现阴影版本化的方法，用于改进编译代码中的指令调度的数据依赖性分析，以及识别要编译的代码内的循环，为每个循环初始化依赖矩阵，每个循环阴影标识由循环访问的符号，检查依赖性，存储，比较和分类依赖向量，生成新的阴影符号，用新的阴影符号替换旧的阴影符号，生成新创建的阴影符号之间的别名关系，调度指令和编译代码。

10. 发明申请

US20090249316A1 COMBINING STATIC AND DYNAMIC COMPILATION TO REMOVE DELINQUENT LOADS 有权
标题翻译：组合静态和动态编译去除负载
公开(公告)号：US20090249316A1
公开(公告)日：2009-10-01
申请号：US12058172
申请日：2008-03-28
申请人： Gheorghe C. Cascaval , Yaoqing Gao , Allan H. Kielstra , Kevin A. Stoodley
发明人： Gheorghe C. Cascaval , Yaoqing Gao , Allan H. Kielstra , Kevin A. Stoodley
IPC分类号： G06F9/45
CPC分类号： G06F8/4442 , G06F12/0862
摘要： A method for combined static and dynamic compilation of program code to remove delinquent loads can include statically compiling source code into executable code with instrumented sections each being suspected of including a delinquent load, and also into a separate intermediate language representation with annotated portions each corresponding to one of the instrumented sections. The method also can include executing the instrumented sections repeatedly and monitoring cache misses for each execution. Finally, the method can include dynamically recompiling selected ones of the instrumented sections using corresponding ones of the annotated portions of the separate intermediate language representation only after a threshold number of executions of the selected ones of the instrumented sections, each recompilation include a pre-fetch directive at a pre-fetch distances tuned to avoid the delinquent load.
摘要翻译：用于组合静态和动态编译程序代码以消除违规负载的方法可以包括将源代码静态编译成可执行代码，其中每个都被怀疑包括拖欠负载的检测部分，以及分别具有注释部分的单独的中间语言表示其中一个仪器部分。该方法还可以包括重复执行检测的部分，并监视每次执行的高速缓存未命中。最后，该方法可以包括仅在所选择的被检测部分的阈值数量执行之后，使用单独的中间语言表示的对应注释部分中的对应的部分动态重新编译所选择的部分部分，每次重新编译包括预取指令以预取距离进行调整，以避免拖欠负荷。

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