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1. 发明申请

US20060048121A1 Method and apparatus for a generic language interface to apply loop optimization transformations 失效
标题翻译：用于通用语言接口的方法和装置，以应用循环优化转换
公开(公告)号：US20060048121A1
公开(公告)日：2006-03-02
申请号：US10926601
申请日：2004-08-26
申请人： Robert Blainey , Arie Tal
发明人： Robert Blainey , Arie Tal
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A generic language interface is provided to apply a number of loop optimization transformations. The language interface includes two new directives. The present invention detects the directives in a computer program, and generates code that has been applied at least one loop transformation based on the directives.
摘要翻译：提供通用语言界面以应用多个循环优化转换。语言界面包括两个新的指令。本发明检测计算机程序中的指令，并且生成已经基于指令应用至少一个循环变换的代码。

2. 发明申请

US20050268039A1 Aggregate bandwidth through store miss management for cache-to-cache data transfer 失效
标题翻译：通过存储管理缓存到缓存数据传输的聚合带宽
公开(公告)号：US20050268039A1
公开(公告)日：2005-12-01
申请号：US10853304
申请日：2004-05-25
申请人： Roch Archambault , Robert Blainey , Yaoging Gao , Randall Heisch , Steven White
发明人： Roch Archambault , Robert Blainey , Yaoging Gao , Randall Heisch , Steven White
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F12/0833 , G06F9/30047 , G06F9/3455 , G06F9/383
摘要： A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse analysis, and performs loop transformations, such as node splitting, loop distribution or stream unrolling to get the proper number of streams. Static prediction and run-time profile information are used to guide loop and stream selection. Compile-time loop cost analysis and run-time check code and versioning are used to determine the number of cache lines ahead of each reference for data cache line zeroing and to tolerate required data alignment relative to data cache lines.
摘要翻译：与底层硬件负载流预取支持协作，通过数据缓存块零（DCBZ）指令减少或避免存储错误的方法和系统，以帮助增加有效的聚合带宽。该方法基于依赖和重用分析在循环中识别和分类唯一流，并执行循环转换，例如节点分割，循环分布或流展开以获得适当数量的流。静态预测和运行时间轮廓信息用于指导循环和流选择。编译时循环成本分析和运行时检查代码和版本控制用于确定数据高速缓存行归零的每个引用之前的高速缓存行数，并允许相对于数据高速缓存行的所需数据对齐。

3. 发明申请

US20050138029A1 Generalized index set splitting in software loops 审中-公开
标题翻译：广义索引集在软件循环中分裂
公开(公告)号：US20050138029A1
公开(公告)日：2005-06-23
申请号：US10864257
申请日：2004-06-09
申请人： Robert Blainey , Arie Tal
发明人： Robert Blainey , Arie Tal
IPC分类号： G06F7/00 , G06F9/44
CPC分类号： G06F8/433
摘要： There is disclosed a method and system for determining the bounds of generated software loops, where the relationships between split points and loop bounds are not known, or only partly known, at compile time. A “sub-range tree” is built with a root node representing the original software loop. Each sub-node represents a sub-range of the original software loop split by one or more split points. Each edge between nodes of the sub-range tree is marked with either a “then” (T) or “else” (E) marker, according to a predetermined scheme. Once the sub-range tree is built, a “path-from-root” is analyzed for each leaf node of the sub-range tree, and “dead” inductive control flow branches are identified and folded. The growth of software loop code based on the sub-range tree may be restricted by a predetermined code growth limit.
摘要翻译：公开了一种用于确定生成的软件循环的边界的方法和系统，其中分割点和循环界限之间的关系在编译时是不知道的，或者仅部分已知的。 “子范围树”用代表原始软件循环的根节点构建。每个子节点表示由一个或多个分割点分割的原始软件循环的子范围。根据预定方案，子范围树的节点之间的每个边缘被标记有“then”（T）或“else”（E）标记。一旦建立了子范围树，就会对子范围树的每个叶节点分析一个“根路径”，并且识别和折叠“死”感应控制流分支。基于子范围树的软件循环码的增长可能受预定代码增长限制。

4. 发明申请

US20050010729A1 Lock caching for compound atomic operations on shared memory 失效
标题翻译：锁定共享内存上复合原子操作的缓存
公开(公告)号：US20050010729A1
公开(公告)日：2005-01-13
申请号：US10864777
申请日：2004-06-08
申请人： Raul Silvera , Robert Blainey
发明人： Raul Silvera , Robert Blainey
IPC分类号： G06F9/22 , G06F9/46 , G06F9/52 , G06F12/00 , G06F12/14 , G06F13/18 , G06F15/167
CPC分类号： G06F9/526 , G06F9/52 , G06F2209/522
摘要： A system and method for lock caching for compound atomic operations (i.e. a read or write operation to more than one 4-byte word) on shared memory is provided. In a computer system including a memory shared among a plurality of processing entities, for example, multiple threads, a method of performing compound atomic operations comprises providing a pool of locks for synchronizing access to the memory; assigning the locks among the plurality of entities to minimize lock contention; and performing the compound atomic operations using the assigned locks. Each lock may be assigned in accordance with an address of the shared memory from the processing entity's compound atomic operations. Assigning locks may be performed in a manner to minimize concurrent atomic updates to the same or overlapping portions of the shared memory. For example, the addresses of the memory from the compound atomic operations may be aliased in accordance with a known upper bound on the amount of the shared memory that may be affected by any atomic operation.
摘要翻译：提供了一种用于复合原子操作的锁定缓存（即，对多于一个4字节字的读取或写入操作）在共享存储器上的系统和方法。在包括在多个处理实体（例如多个线程）中共享的存储器的计算机系统中，执行复合原子操作的方法包括提供用于同步对存储器的访问的锁存池; 在多个实体之间分配锁以最小化锁争用; 并使用分配的锁执行复合原子操作。可以根据来自处理实体的复合原子操作的共享存储器的地址来分配每个锁。可以以使共享存储器的相同或重叠部分的并发原子更新最小化的方式来执行分配锁定。例如，来自复合原子操作的存储器的地址可以根据可能受任何原子操作影响的共享存储器的量的已知上限进行别名。

5. 发明申请

US20080028381A1 OPTIMIZING SOURCE CODE FOR ITERATIVE EXECUTION 审中-公开
标题翻译：优化源代码进行迭代执行
公开(公告)号：US20080028381A1
公开(公告)日：2008-01-31
申请号：US11870121
申请日：2007-10-10
申请人： ROCH ARCHAMBAULT , ROBERT BLAINEY , CHARLES HALL , YINGWEI ZHANG
发明人： ROCH ARCHAMBAULT , ROBERT BLAINEY , CHARLES HALL , YINGWEI ZHANG
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： An embodiment of the present invention provides an optimizer for optimizing source code to generate optimized source code having instructions for instructing a central processing unit (CPU) to iteratively compute values for a primary recurrence element. A computer programmed loop for computing the primary recurrence element and subsequent recurrence elements is an example of a case involving iteratively computing the primary recurrence element. The CPU is operatively coupled to fast operating memory (FOM) and operatively coupled to slow operating memory (SOM). SOM stores the generated optimized source code. The optimized source code includes instructions for instructing said CPU to store a computed value of the primary recurrence element in a storage location of FOM. The instructions also includes instructions to consign the computed value of the primary recurrence element from the storage location to another storage location of the FOM.
摘要翻译：本发明的一个实施例提供一种用于优化源代码以产生优化的源代码的优化器，其具有用于指示中央处理单元（CPU）迭代地计算初级重复元件的值的指令。用于计算主要递归元素和随后的递归元素的计算机编程回路是涉及迭代地计算主要复发元素的情况的示例。 CPU可操作地耦合到快速操作存储器（FOM）并且可操作地耦合到慢速操作存储器（SOM）。 SOM存储生成的优化源代码。优化的源代码包括用于指示所述CPU将计算的主循环元素的值存储在FOM的存储位置中的指令。指令还包括将计算的主循环元素的值从存储位置委托给FOM的另一个存储位置的指令。

6. 发明申请

US20060047734A1 Fast conversion of integer to float using table lookup 审中-公开
标题翻译：使用表查找快速将整数转换为浮点数
公开(公告)号：US20060047734A1
公开(公告)日：2006-03-02
申请号：US10929192
申请日：2004-08-30
申请人： Robert Blainey , Shimin Cui , Mark Mendell , Steven White
发明人： Robert Blainey , Shimin Cui , Mark Mendell , Steven White
IPC分类号： G06F7/00
CPC分类号： H03M7/24
摘要： Method, system and computer program product for converting integers to floating point values in a data processing system. The method utilizes data flow analysis and control flow analysis to recognize that a particular integer that is to be converted contains only a limited range of values. Knowledge of this limited range is used to establish a table of floating point values indexed by the integer value. By using the table of floating point values, conversion of an integer to a floating point value can be performed faster and with reduced memory traffic.
摘要翻译：用于在数据处理系统中将整数转换为浮点值的方法，系统和计算机程序产品。该方法利用数据流分析和控制流分析来识别要转换的特定整数仅包含有限的值范围。知道此有限范围用于建立由整数值索引的浮点值表。通过使用浮点值表，可以更快地执行整数转换为浮点值并减少内存流量。

7. 发明申请

US20050138613A1 Method and system for code modification based on cache structure 失效
标题翻译：基于缓存结构的代码修改方法和系统
公开(公告)号：US20050138613A1
公开(公告)日：2005-06-23
申请号：US10855729
申请日：2004-05-27
申请人： Roch Archambault , Robert Blainey , Yaoqing Gao , John McCalpin , Francis O'Connell , Pascal Vezolle , Steven White
发明人： Roch Archambault , Robert Blainey , Yaoqing Gao , John McCalpin , Francis O'Connell , Pascal Vezolle , Steven White
IPC分类号： G06F9/44 , G06F9/45 , G06F12/02
CPC分类号： G06F8/4442
摘要： A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining static and dynamic characteristics for the instructions; selecting a modification factor for the instructions based on a number of separate equivalent sections forming a cache in a processor which is processing the instructions; and modifying the instructions to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.
摘要翻译：提供了修改形成循环的指令的方法和系统。修改形成循环的指令的方法包括修改形成循环的指令，包括：确定指令的静态和动态特性; 基于在正在处理所述指令的处理器中形成高速缓存的单独的等效部分的数量来选择所述指令的修改因子; 以及当指令满足基于静态和动态特性的修改标准时，修改指令以根据修改因子和静态和动态特性来交织循环中的指令。

8. 发明申请

US20060048120A1 Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations 失效
公开(公告)号：US20060048120A1
公开(公告)日：2006-03-02
申请号：US10926595
申请日：2004-08-26
申请人： Rock Archambault , Robert Blainey , Yaoqing Gao , Allan Martin , James McInnes , Francis O'Connell
发明人： Rock Archambault , Robert Blainey , Yaoqing Gao , Allan Martin , James McInnes , Francis O'Connell
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.

9. 发明申请

US20050246700A1 Compiler with cache utilization optimizations 失效
标题翻译：具有缓存利用率优化的编译器
公开(公告)号：US20050246700A1
公开(公告)日：2005-11-03
申请号：US10835756
申请日：2004-04-30
申请人： Roch Archambault , Robert Blainey , Yaoqing Gao
发明人： Roch Archambault , Robert Blainey , Yaoqing Gao
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A compiling program with cache utilization optimizations employs an inter-procedural global analysis of the data access patterns of compile units to be processed. The global analysis determines sufficient information to allow intelligent application of optimization techniques to be employed to enhance the operation and utilization of the available cache systems on target hardware.
摘要翻译：具有缓存利用率优化的编译程序采用对要处理的编译单元的数据访问模式的跨过程全局分析。全局分析确定足够的信息，以允许智能应用优化技术来增强目标硬件上可用的高速缓存系统的操作和利用。

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