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1. 发明申请

US20070088937A1 Computer-implemented method and processing unit for predicting branch target addresses 审中-公开
标题翻译：用于预测分支目标地址的计算机实现的方法和处理单元
公开(公告)号：US20070088937A1
公开(公告)日：2007-04-19
申请号：US11250057
申请日：2005-10-13
申请人： Roch Archambault , R. Hay , James McInnes , Kevin Stoodley
发明人： Roch Archambault , R. Hay , James McInnes , Kevin Stoodley
IPC分类号： G06F9/00
CPC分类号： G06F9/30058 , G06F9/3806
摘要： Under the present invention, a branch target address corresponding to a target instruction to be pre-fetched is predicted based on two values. The first value is a “predictor value” that is known for the branch target address. The second value is the address of the branch instruction from which the target instruction is branched to within the program code. Once these two values are provided, they can be processed (e.g., hashed) to yield an index value, which is used to obtain a predicted branch target address from a cache. This technique is generally implemented for branch instructions such as switch statements or polymorphic calls. In the case of the former, the predictor value is a selector operand, while in the case of the latter the predictor value is a class object address (in JAVA) or a virtual function table address (in C++).
摘要翻译：在本发明中，基于两个值预测与预取的目标指令对应的分支目标地址。第一个值是分支目标地址已知的“预测值”。第二个值是目标指令从该程序代码中分支到的分支指令的地址。一旦提供了这两个值，就可以对它们进行处理（例如，散列）以产生索引值，该索引值用于从高速缓存获得预测的分支目标地址。这种技术通常用于分支指令，例如switch语句或多态调用。在前者的情况下，预测值是一个选择器操作数，而在后者的情况下，预测值是类对象地址（在JAVA中）或虚函数表地址（C ++中）。

2. 发明申请

US20060048111A1 Method and apparatus for determining the profitability of expanding unpipelined instructions 失效
公开(公告)号：US20060048111A1
公开(公告)日：2006-03-02
申请号：US10930042
申请日：2004-08-30
申请人： Roch Archambault , Robert Enenkel , Robert Hay , Allan Martin , James McInnes , Ronald McIntosh , Mark Mendell
发明人： Roch Archambault , Robert Enenkel , Robert Hay , Allan Martin , James McInnes , Ronald McIntosh , Mark Mendell
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A method, apparatus, and computer instructions for processing instructions. A data dependency graph is built. The data dependency graph is analyzed for recurrences, and unpipelined instructions that lie outside of the recurrences are expanded.

3. 发明申请

US20070088915A1 Method and apparatus for software-assisted data cache and prefetch control 有权
标题翻译：用于软件辅助数据缓存和预取控制的方法和装置
公开(公告)号：US20070088915A1
公开(公告)日：2007-04-19
申请号：US11250054
申请日：2005-10-13
申请人： Roch Archambault , Yaoqing Gao , Francis O' Connell , Robert Tremaine , Michael Wazlowski , Steven White , Lixin Zhang
发明人： Roch Archambault , Yaoqing Gao , Francis O' Connell , Robert Tremaine , Michael Wazlowski , Steven White , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F9/3879 , G06F8/4442 , G06F9/30047 , G06F9/3455 , G06F12/0862 , G06F2212/6028
摘要： The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.
摘要翻译：本发明提供了一种用于编译用于管理高速缓存系统的指令的计算机实现的方法，装置和计算机可用程序代码。分析循环结构以识别指令中的缓存和预取条件的数据使用特征以形成识别的预取条件。基于数据使用特性和识别的预取条件将一组控制指令插入到指令中以形成多个修改的指令。编译多组修改指令的集合以生成用于执行的代码以形成编译指令。编译指令中的一组控制指令形成高速缓存管理策略以在执行编译指令期间控制存储器系统中数据的移动。

4. 发明授权

US07380086B2 Scalable runtime system for global address space languages on shared and distributed memory machines 有权
标题翻译：可扩展运行时系统，用于共享和分布式内存机器上的全局地址空间语言
公开(公告)号：US07380086B2
公开(公告)日：2008-05-27
申请号：US10734690
申请日：2003-12-12
申请人： Roch Archambault , Anthony Simon Bolmarcich , G. Calin Cascaval , Siddhartha Chatterjee , Maria Eleftheriou , Raymond Mak
发明人： Roch Archambault , Anthony Simon Bolmarcich , G. Calin Cascaval , Siddhartha Chatterjee , Maria Eleftheriou , Raymond Mak
IPC分类号： G06F12/00 , G06F9/45 , G06F9/46
CPC分类号： G06F9/5016
摘要： An improved scalability runtime system for a global address space language running on a distributed or shared memory machine uses a directory of shared variables having a data structure for tracking shared variable information that is shared by a plurality of program threads. Allocation and de-allocation routines are used to allocate and de-allocate shared variable entries in the directory of shared variables. Different routines can be used to access different types of shared data. A control structure is used to control access to the shared data such that all threads can access the data at any time. Since all threads see the same objects, synchronization issues are eliminated. In addition, the improved efficiency of the data sharing allows the number of program threads to be vastly increased.
摘要翻译：用于在分布式或共享存储器机器上运行的全局地址空间语言的改进的可扩展性运行时系统使用具有用于跟踪由多个程序线程共享的共享变量信息的数据结构的共享变量的目录。分配和解除分配例程用于在共享变量目录中分配和取消分配共享变量条目。可以使用不同的例程来访问不同类型的共享数据。控制结构用于控制对共享数据的访问，以便所有线程可以随时访问数据。由于所有线程都看到相同的对象，因此消除了同步问题。另外，提高数据共享的效率使得程序线程的数量大大增加。

5. 发明申请

US20050080981A1 Structure and method for managing workshares in a parallel region 审中-公开
标题翻译：并行区管理工作的结构和方法
公开(公告)号：US20050080981A1
公开(公告)日：2005-04-14
申请号：US10845553
申请日：2004-05-13
申请人： Roch Archambault , Raul Silvera , Guansong Zhang
发明人： Roch Archambault , Raul Silvera , Guansong Zhang
IPC分类号： G06F9/38 , G06F9/50 , G06F15/76 , G11C5/00
CPC分类号： G06F9/5066
摘要： A data processing system is adapted to execute at least one workshare construct in a parallel region. The data processing system uses at least one thread for executing a corresponding subsection of the workshare construct and provides control blocks for managing corresponding workshare constructs in the parallel region. A method of managing the control blocks comprises: adding an array of control blocks to a control block queue; assigning control blocks in the initialized array to corresponding workshare constructs in the parallel region until a barrier is reached; and waiting at the barrier for all threads in the parallel region to complete their corresponding subsections and then resetting the control block to the beginning of the control block queue. Also provided are a computer program product and a data processing system for implementing the method.
摘要翻译：数据处理系统适于在并行区域中执行至少一个作业分配构造。数据处理系统使用至少一个线程来执行工作共享结构的相应子部分，并且提供用于管理并行区域中的相应作业分配构造的控制块。一种管理控制块的方法包括：将一组控制块添加到控制块队列; 将初始化的数组中的控制块分配给并行区域中的相应的工作区构造，直到达到屏障; 并且在并行区域中的所有线程等待屏障以完成其对应的子部分，然后将控制块重置为控制块队列的开头。还提供了一种用于实现该方法的计算机程序产品和数据处理系统。

6. 发明申请

US20060048118A1 Method and apparatus for optimizing code with artificial statements 审中-公开
标题翻译：用人造语句优化代码的方法和装置
公开(公告)号：US20060048118A1
公开(公告)日：2006-03-02
申请号：US10930041
申请日：2004-08-30
申请人： Roch Archambault , Peng Zhao
发明人： Roch Archambault , Peng Zhao
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A method, apparatus, and computer instructions for facilitating optimization of code. An artificial statement is placed into the code. The artificial statement encodes information. The code is optimized with a compiler. The compiler performs an action based on the artificial statement in the code.
摘要翻译：一种用于促进代码优化的方法，装置和计算机指令。代码中放置了一个人工语句。人工语句对信息进行编码。代码使用编译器进行了优化。编译器根据代码中的人工语句执行一个操作。

7. 发明申请

US20060048117A1 Method and apparatus for optimizing software program using inter-procedural strength reduction 失效
标题翻译：使用程序间强度降低优化软件程序的方法和装置
公开(公告)号：US20060048117A1
公开(公告)日：2006-03-02
申请号：US10930038
申请日：2004-08-30
申请人： Roch Archambault , Shimin Cui , Raul Silvera
发明人： Roch Archambault , Shimin Cui , Raul Silvera
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： Inter-procedural strength reduction is provided by a mechanism of the present invention to optimize software program. During a forward pass, the present invention collects information of global variables and analyzes the information to select candidate computations for optimization. During a backward pass, the present invention replaces costly computations with less costly or weaker computations using pre-computed values and inserts store operations of new global variables to pre-compute the costly computations at definition points of the global variables used in the costly computations.
摘要翻译：通过本发明的机制来优化软件程序来提供程序间强度降低。在正向通过期间，本发明收集全局变量的信息并分析该信息以选择用于优化的候选计算。在反向传递期间，本发明使用预先计算的值替代使用成本较低或较弱计算的昂贵的计算，并插入新的全局变量的存储操作，以在昂贵的计算中使用的全局变量的定义点处预先计算昂贵的计算。

8. 发明申请

US20050268039A1 Aggregate bandwidth through store miss management for cache-to-cache data transfer 失效
标题翻译：通过存储管理缓存到缓存数据传输的聚合带宽
公开(公告)号：US20050268039A1
公开(公告)日：2005-12-01
申请号：US10853304
申请日：2004-05-25
申请人： Roch Archambault , Robert Blainey , Yaoging Gao , Randall Heisch , Steven White
发明人： Roch Archambault , Robert Blainey , Yaoging Gao , Randall Heisch , Steven White
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F12/0833 , G06F9/30047 , G06F9/3455 , G06F9/383
摘要： A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse analysis, and performs loop transformations, such as node splitting, loop distribution or stream unrolling to get the proper number of streams. Static prediction and run-time profile information are used to guide loop and stream selection. Compile-time loop cost analysis and run-time check code and versioning are used to determine the number of cache lines ahead of each reference for data cache line zeroing and to tolerate required data alignment relative to data cache lines.
摘要翻译：与底层硬件负载流预取支持协作，通过数据缓存块零（DCBZ）指令减少或避免存储错误的方法和系统，以帮助增加有效的聚合带宽。该方法基于依赖和重用分析在循环中识别和分类唯一流，并执行循环转换，例如节点分割，循环分布或流展开以获得适当数量的流。静态预测和运行时间轮廓信息用于指导循环和流选择。编译时循环成本分析和运行时检查代码和版本控制用于确定数据高速缓存行归零的每个引用之前的高速缓存行数，并允许相对于数据高速缓存行的所需数据对齐。

9. 发明申请

US20070240137A1 Method of compiling source code 失效
标题翻译：编译源代码的方法
公开(公告)号：US20070240137A1
公开(公告)日：2007-10-11
申请号：US11402556
申请日：2006-04-11
申请人： Roch Archambault , Shimin Cui , Yaoqing Gao , Raul Silvera
发明人： Roch Archambault , Shimin Cui , Yaoqing Gao , Raul Silvera
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A method of compiling source code. The method includes converting pointer-based access in the source code to array-based access in the source code in a first pass compilation of the source code. Information is collected for objects in the source code during the first pass compilation. Candidate objects in the source code are selected based on the collected information to form selected candidate objects. Global stride variables are created for the selected candidate objects. Memory allocation operations are updated for the selected candidate objects in a second pass compilation of the source code. Multiple-level pointer indirect references are replaced in the source code with multi-dimensional array indexed references for the selected candidate objects in the second pass compilation of the source code.
摘要翻译：一种编译源代码的方法。该方法包括在源代码的第一遍编译中将源代码中的基于指针的访问转换为源代码中的基于数组的访问。在第一次编译期间，为源代码中的对象收集信息。基于收集的信息来选择源代码中的候选对象以形成所选择的候选对象。为所选候选对象创建全局步幅变量。在源代码的第二遍编译中，针对所选候选对象更新内存分配操作。在源代码的第二遍编译中，多级指针间接引用被替换为所选候选对象的多维数组索引引用的源代码。

10. 发明申请

US20060048103A1 Method and apparatus for improving data cache performance using inter-procedural strength reduction of global objects 失效
公开(公告)号：US20060048103A1
公开(公告)日：2006-03-02
申请号：US10930037
申请日：2004-08-30
申请人： Roch Archambault , Shimin Cui , Yaoqing Gao , Raul Silvera
发明人： Roch Archambault , Shimin Cui , Yaoqing Gao , Raul Silvera
IPC分类号： G06F9/44
CPC分类号： G06F8/4442
摘要： Inter-procedural strength reduction is provided by a mechanism of the present invention to improve data cache performance. During a forward pass, the present invention collects information of global variables and analyzes the usage pattern of global objects to select candidate computations for optimization. During a backward pass, the present invention remaps global objects into smaller size new global objects and generates more cache efficient code by replacing candidate computations with indirect or indexed reference of smaller global objects and inserting store operations to the new global objects for each computation that references the candidate global objects.

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