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1. 发明授权

US07940575B2 Memory device and method providing logic connections for data transfer 有权
标题翻译：提供用于数据传输的逻辑连接的存储器件和方法
公开(公告)号：US07940575B2
公开(公告)日：2011-05-10
申请号：US12058191
申请日：2008-03-28
申请人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
发明人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
IPC分类号： G11C7/10 , G11C8/12 , G11C16/06
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.
摘要翻译：在一个实施例中，提供了一种用于在存储器件中传送数据的方法。该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。数据通过使用可控连接的逻辑连接进行传输。同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

2. 发明申请

US20090244949A1 Memory Device and Method Providing Logic Connections for Data Transfer 有权
标题翻译：为数据传输提供逻辑连接的存储器件和方法
公开(公告)号：US20090244949A1
公开(公告)日：2009-10-01
申请号：US12058191
申请日：2008-03-28
申请人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
发明人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
IPC分类号： G11C5/06
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.
摘要翻译：在一个实施例中，提供了一种用于在存储器件中传送数据的方法。该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。数据通过使用可控连接的逻辑连接进行传输。同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

3. 发明授权

US07602649B2 Method of operating an integrated circuit for reading the logical state of a memory cell 有权
标题翻译：操作用于读取存储器单元的逻辑状态的集成电路的方法
公开(公告)号：US07602649B2
公开(公告)日：2009-10-13
申请号：US11849828
申请日：2007-09-04
申请人： Josef Willer , Detlev Richter
发明人： Josef Willer , Detlev Richter
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/26
摘要： In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided.
摘要翻译：在本发明的实施例中，提供了一种操作用于读取集成电路中的存储单元串中包括的多个存储单元中选定的一个的逻辑状态的集成电路的方法。

4. 发明申请

US20090097317A1 Integrated Circuit Having NAND Memory Cell Strings 有权
标题翻译：具有NAND存储器单元串的集成电路
公开(公告)号：US20090097317A1
公开(公告)日：2009-04-16
申请号：US11872655
申请日：2007-10-15
申请人： Josef Willer , Franz Hofmann , Detlev Richter , Nicolas Nagel
发明人： Josef Willer , Franz Hofmann , Detlev Richter , Nicolas Nagel
IPC分类号： G11C16/00 , H01L21/336 , H01L29/788
CPC分类号： G11C16/0483 , G11C16/0475 , H01L27/115 , H01L27/11565 , H01L27/11568
摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.
摘要翻译：本发明的实施例一般涉及用于制造集成电路的集成电路和方法。在本发明的实施例中，提供了具有存储单元的集成电路。存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区旁边的沟槽。

5. 发明申请

US20090059673A1 Method of Operating an Integrated Circuit for Reading the Logical State of a Memory Cell 有权
标题翻译：操作用于读取存储器单元的逻辑状态的集成电路的方法
公开(公告)号：US20090059673A1
公开(公告)日：2009-03-05
申请号：US11849828
申请日：2007-09-04
申请人： Josef Willer , Detlev Richter
发明人： Josef Willer , Detlev Richter
IPC分类号： G11C16/26
CPC分类号： G11C16/0483 , G11C16/26
摘要： In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided.
摘要翻译：在本发明的实施例中，提供了一种操作用于读取集成电路中的存储单元串中包括的多个存储单元中选定的一个的逻辑状态的集成电路的方法。

6. 发明申请

US20080080226A1 Memory system and method of operating the memory system 审中-公开
标题翻译：内存系统和操作内存系统的方法
公开(公告)号：US20080080226A1
公开(公告)日：2008-04-03
申请号：US11526850
申请日：2006-09-25
申请人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
发明人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/5614 , G11C7/1006 , G11C7/22 , G11C11/16 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2207/107 , G11C2211/5641
摘要： A memory system includes a plurality of resistive memory cell fields including at least a first resistive memory cell field and a second resistive memory cell field, the first resistive memory cell field formed with a plurality of resistive memory cells storing data at a first data storage speed, the second resistive memory cell field formed with a plurality of resistive memory cells storing data at a second data storage speed lower than the first data storage speed, and a controller controlling data transfer between the plurality of resistive memory cell fields.
摘要翻译：存储器系统包括多个电阻存储单元区域，至少包括第一电阻存储单元区域和第二电阻存储单元区域，第一电阻存储单元区域形成有多个电阻存储单元，以第一数据存储速度存储数据形成有以低于第一数据存储速度的第二数据存储速度存储数据的多个电阻性存储单元形成的第二电阻性存储单元区域，以及控制器，用于控制多个电阻性存储单元区域之间的数据传输。

7. 发明授权

US07778073B2 Integrated circuit having NAND memory cell strings 有权
标题翻译：具有NAND存储单元串的集成电路
公开(公告)号：US07778073B2
公开(公告)日：2010-08-17
申请号：US11872655
申请日：2007-10-15
申请人： Josef Willer , Franz Hofmann , Detlev Richter , Nicolas Nagel
发明人： Josef Willer , Franz Hofmann , Detlev Richter , Nicolas Nagel
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/0475 , H01L27/115 , H01L27/11565 , H01L27/11568
摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.
摘要翻译：本发明的实施例一般涉及用于制造集成电路的集成电路和方法。在本发明的实施例中，提供了具有存储单元的集成电路。存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区旁边的沟槽。

8. 发明申请

US20100019345A1 Integrated Circuit with an Active Area Line Having at Least One Form-Supporting Element and Corresponding Method of Making an Integrated Circuit 有权
标题翻译：具有至少一个支撑元件的有源面积线的集成电路和制造集成电路的相应方法
公开(公告)号：US20100019345A1
公开(公告)日：2010-01-28
申请号：US12177930
申请日：2008-07-23
申请人： Josef Willer , Michael Specht , Christoph Friederich , Doris Keitel-Schulz
发明人： Josef Willer , Michael Specht , Christoph Friederich , Doris Keitel-Schulz
IPC分类号： H01L21/3065 , H01L23/58
CPC分类号： H01L21/28273 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.
摘要翻译：描述了集成电路。集成电路可以具有：由具有与半导体衬底的上表面平行的第一纵向方向的半导体衬底的材料形成的有源区线; 其中所述有源面积线具有至少一个形状支撑元件，所述支撑元件在平行于所述半导体衬底的上表面的第二纵向方向上延伸; 并且其中所述第二纵向方向相对于所述第一纵向方向以不等于0度并且不等于180度的角度布置。

9. 发明申请

US20090261397A1 Integrated Circuit with Floating-Gate Electrodes Including a Transition Metal and Corresponding Manufacturing Method 有权
标题翻译：具有过渡金属的浮栅电极集成电路及相应的制造方法
公开(公告)号：US20090261397A1
公开(公告)日：2009-10-22
申请号：US12104750
申请日：2008-04-17
申请人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
发明人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11521
摘要： An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.
摘要翻译：描述了集成电路。集成电路可以包括多个浮栅电极，其中浮栅电极中的至少一个具有较低宽度和上宽度，下宽度大于上宽度，并且其中至少一个浮栅电极包括过渡金属。还描述了集成电路的相应制造方法。

10. 发明申请

US20090251968A1 Integrated circuit having a base structure and a nanostructure 审中-公开
标题翻译：具有基底结构和纳米结构的集成电路
公开(公告)号：US20090251968A1
公开(公告)日：2009-10-08
申请号：US12099522
申请日：2008-04-08
申请人： Christoph Andreas Kleint , Josef Willer
发明人： Christoph Andreas Kleint , Josef Willer
IPC分类号： H01L21/00 , G11C16/04
CPC分类号： H01L27/11578 , H01L27/11582
摘要： In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure.
摘要翻译：在一个实施例中，集成电路可以包括金属导电结构，具有晶体取向的基底结构，与金属导电结构相邻的基底结构，以及设置在基底结构上的纳米结构，纳米结构具有基本上相同的晶体取向作为基础结构。

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