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1. 发明授权

US06836808B2 Pipelined packet processing 失效
标题翻译：流水线包处理
公开(公告)号：US06836808B2
公开(公告)日：2004-12-28
申请号：US09683863
申请日：2002-02-25
申请人： Robert Michael Bunce , Christos John Georgiou , Valentina Salapura
发明人： Robert Michael Bunce , Christos John Georgiou , Valentina Salapura
IPC分类号： G06F300
CPC分类号： H04L49/1546 , H04L49/103 , H04L49/3018 , H04L49/357 , H04L49/90
摘要： A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet processing tasks for processing a single packet are performed on multiple processors or threads, acting as stages of a pipeline. The assignment of tasks to processors or threads is performed dynamically, by checking the availability of a processor or thread in the subsequent pipeline stage. The availability determination includes determining the available capacity of the input work queue associated with each processor or thread. If the subsequent pipeline stage is overloaded, the task is assigned to another processor or thread that is not overloaded.
摘要翻译：一种用于提高分组协议处理程序内的分组处理效率的方法和系统。根据本发明的方法，在多个处理器或线程上同时并以流水线方式执行分组处理任务。用于处理单个分组的后续协议分组处理任务在作为流水线的阶段的多个处理器或线程上执行。通过检查后续流水线阶段中的处理器或线程的可用性，动态地对处理器或线程分配任务。可用性确定包括确定与每个处理器或线程相关联的输入工作队列的可用容量。如果随后的流水线阶段过载，则将任务分配给另一个未重载的处理器或线程。

2. 发明授权

US07003597B2 Dynamic reallocation of data stored in buffers based on packet size 失效
标题翻译：基于数据包大小动态重新分配存储在缓冲区中的数据
公开(公告)号：US07003597B2
公开(公告)日：2006-02-21
申请号：US10604295
申请日：2003-07-09
申请人： Christos John Georgiou , Valentina Salapura
发明人： Christos John Georgiou , Valentina Salapura
IPC分类号： G06F12/02
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9052
摘要： A method and system is provided to efficiently manage memory in a network device that receives packets of variable size. The memory is allocated into portions whereby each portion, comprising multiple equally-sized buffers, receives packets of a particular size. One portion is used for smaller packet sizes and another portion is for larger packet sizes, although other portions may be created. As packets are received at the network device, they are stored into the appropriate memory portion based on their size. The number of available buffers in each portion is monitored so that, when it falls below a threshold, buffers are reallocated to the other thereby increasing the overall memory efficiency.
摘要翻译：提供了一种方法和系统来有效地管理接收可变大小的分组的网络设备中的存储器。存储器被分配到部分，由此包括多个相等大小的缓冲器的每个部分接收特定大小的分组。一部分用于较小的分组大小，另一部分用于较大的分组大小，但可以创建其他部分。当在网络设备处接收到分组时，它们基于它们的大小被存储到适当的存储器部分中。监视每个部分中的可用缓冲器的数量，使得当其低于阈值时，缓冲器被重新分配到另一个，从而增加整体存储器效率。

3. 发明授权

US10078515B2 Tracking operand liveness information in a computer system and performing function based on the liveness information 有权
公开(公告)号：US10078515B2
公开(公告)日：2018-09-18
申请号：US13251441
申请日：2011-10-03
申请人： Michael K Gschwind , Valentina Salapura
发明人： Michael K Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38 , G06F9/40 , G06F9/46
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/30105 , G06F9/30127 , G06F9/30185 , G06F9/3832 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/462
摘要： Operand liveness state information is maintained during context switches for current architected operands of executing programs. The current operand state information indicates whether corresponding current operands are enabled or disabled for use by a first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands. A machine instruction of the first program module accesses a current operand by using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.

4. 发明授权

US09727336B2 Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers 有权
公开(公告)号：US09727336B2
公开(公告)日：2017-08-08
申请号：US13234785
申请日：2011-09-16
申请人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
发明人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/3013 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30189
摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

5. 发明授权

US09329869B2 Prefix computer instruction for compatibily extending instruction functionality 有权
标题翻译：前缀计算机指令，用于兼容扩展指令功能
公开(公告)号：US09329869B2
公开(公告)日：2016-05-03
申请号：US13251426
申请日：2011-10-03
申请人： Michael K Gschwind , Valentina Salapura
发明人： Michael K Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38 , G06F9/34
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30185 , G06F9/34 , G06F9/3826 , G06F9/384
摘要： A prefix instruction is executed and passes operands to a net instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a target register of the prefix instruction execution.
摘要翻译：执行前缀指令并将操作数传递到网络指令而不将操作数存储在架构资源中，使得下一条指令的执行使用由前缀指令提供的操作数来执行操作，操作数可以是前缀指令立即字段或前缀指令执行的目标寄存器。

6. 发明授权

US09098408B2 Ticket consolidation for multi-tiered applications 有权
公开(公告)号：US09098408B2
公开(公告)日：2015-08-04
申请号：US13592578
申请日：2012-08-23
申请人： Ruchi Mahindru , Valentina Salapura
发明人： Ruchi Mahindru , Valentina Salapura
IPC分类号： G06F11/00 , G06F11/07 , G06F11/34
CPC分类号： G06F11/07 , G06F11/0709 , G06F11/0784 , G06F11/34 , G06Q10/103 , G06Q10/20
摘要： Consolidating problem tickets for a multi-tiered application may comprise identifying a plurality of correlated virtual machines that are running one or more application components of the multi-tiered application. Problem reports may be identified that are generated by one or more of the plurality of correlated virtual machines and caused by a failure of a same single component of the multi-tiered application. The identified problem reports may be consolidated into a single ticket and placed into a ticket handling system.

7. 发明授权

US08904392B2 Shared performance monitor in a multiprocessor system 有权
标题翻译：多处理器系统中的共享性能监视器
公开(公告)号：US08904392B2
公开(公告)日：2014-12-02
申请号：US13484797
申请日：2012-05-31
申请人： George Chiu , Alan G. Gara , Valentina Salapura
发明人： George Chiu , Alan G. Gara , Valentina Salapura
IPC分类号： G06F9/46 , G06F11/34
CPC分类号： G06F11/348 , G06F11/3409 , G06F2201/86 , G06F2201/88 , Y02D10/34
摘要： A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.
摘要翻译：用于监视在多处理器系统中发生的事件的性能的性能监视单元（PMU）和方法。多处理器系统包括多个处理器设备单元，用于产生表示处理器设备中事件发生的信号的每个处理器设备，以及用于性能监控的单个共享计数器资源。性能监视器单元由多处理器系统中的所有处理器核共享。 PMU进一步被编程为监视从非处理器设备发出的事件信号。

8. 发明授权

US08904153B2 Vector loads with multiple vector elements from a same cache line in a scattered load operation 有权
标题翻译：在分散加载操作中，来自相同高速缓存行的多个向量元素的向量加载
公开(公告)号：US08904153B2
公开(公告)日：2014-12-02
申请号：US12876321
申请日：2010-09-07
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/345 , G06F9/30 , G06F9/38 , G06F15/80
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3857 , G06F15/8069
摘要： Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of data element address portions that specify a plurality of data elements to be accessed using the single extended address. Each of the plurality of data element address portions is provided to corresponding data element selector logic units of the cache memory. Each data element selector logic unit in the cache memory selects a corresponding data element from a cache line buffer based on a corresponding data element address portion provided to the data element selector logic unit. Each data element selector logic unit outputs the corresponding data element for use by the processor.
摘要翻译：提供了执行分散加载操作的机构。利用这些机制，扩展地址被接收在处理器的高速缓冲存储器中。扩展地址具有多个数据元素地址部分，其指定使用单个扩展地址来访问的多个数据元素。多个数据元素地址部分中的每一个被提供给高速缓冲存储器的相应数据元素选择器逻辑单元。高速缓冲存储器中的每个数据元素选择器逻辑单元基于提供给数据元素选择器逻辑单元的相应数据元素地址部分从高速缓存行缓冲器中选择相应的数据元素。每个数据元素选择器逻辑单元输出相应的数据元素供处理器使用。

9. 发明授权

US08904118B2 Mechanisms for efficient intra-die/intra-chip collective messaging 有权
标题翻译：有效的片内/片内集体消息传递的机制
公开(公告)号：US08904118B2
公开(公告)日：2014-12-02
申请号：US12986528
申请日：2011-01-07
申请人： Amith R. Mamidala , Valentina Salapura , Robert W. Wisniewski
发明人： Amith R. Mamidala , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/10 , G06F12/08 , G06F15/167
CPC分类号： G06F12/0831 , G06F15/167
摘要： Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains.
摘要翻译：提供了具有单独的共享存储器一致性域的节点之间的有效模内集体处理的机制。集成电路管芯可以包括在集成电路管芯上实现的硬件集合单元。集成电路管芯上的多个核被分组成多个共享存储器相干域。多个共享存储器相干域中的每一个连接到集体单元，用于在多个共享存储器相干域之间执行集合操作。

10. 发明授权

US08811422B2 Single chip protocol converter 有权
标题翻译：单芯片协议转换器
公开(公告)号：US08811422B2
公开(公告)日：2014-08-19
申请号：US13269065
申请日：2011-10-07
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/16 , G06F15/167 , H04L12/56 , G06F15/78
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单一集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

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