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1. 发明授权

US5757682A Parallel calculation of exponent and sticky bit during normalization 失效
标题翻译：在归一化期间并行计算指数和粘点
公开(公告)号：US5757682A
公开(公告)日：1998-05-26
申请号：US414072
申请日：1995-03-31
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional dataflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.
摘要翻译：根据分数位移数据流，根据将指数分解成部分指数组，实现用于在归一化期间确定分数移位的方法来确定指数的方法的系统，根据分数确定每个部分指数组的所有可能的部分指数值数据流，并且通过根据分数据流选择性地组合来自每个部分指数组的可能部分指数来提供指数。还提供了一种实现在归一化过程中产生粘性位的方法的系统。粘滞位信息根据分数据流进行预先计算和复用。在本发明的一个实施例中，以树形式计算组粘性信号，每组粘性具有与多路复用的移位增量量相对应的多个可能的粘性位。组粘性位根据分数据流中的随后的移位量进一步复用，以在与最终分数移位量可用时基本相同的时间提供输出粘性位，并且因此与归一化分数基本上相同。

2. 发明授权

US06836808B2 Pipelined packet processing 失效
标题翻译：流水线包处理
公开(公告)号：US06836808B2
公开(公告)日：2004-12-28
申请号：US09683863
申请日：2002-02-25
申请人： Robert Michael Bunce , Christos John Georgiou , Valentina Salapura
发明人： Robert Michael Bunce , Christos John Georgiou , Valentina Salapura
IPC分类号： G06F300
CPC分类号： H04L49/1546 , H04L49/103 , H04L49/3018 , H04L49/357 , H04L49/90
摘要： A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet processing tasks for processing a single packet are performed on multiple processors or threads, acting as stages of a pipeline. The assignment of tasks to processors or threads is performed dynamically, by checking the availability of a processor or thread in the subsequent pipeline stage. The availability determination includes determining the available capacity of the input work queue associated with each processor or thread. If the subsequent pipeline stage is overloaded, the task is assigned to another processor or thread that is not overloaded.
摘要翻译：一种用于提高分组协议处理程序内的分组处理效率的方法和系统。根据本发明的方法，在多个处理器或线程上同时并以流水线方式执行分组处理任务。用于处理单个分组的后续协议分组处理任务在作为流水线的阶段的多个处理器或线程上执行。通过检查后续流水线阶段中的处理器或线程的可用性，动态地对处理器或线程分配任务。可用性确定包括确定与每个处理器或线程相关联的输入工作队列的可用容量。如果随后的流水线阶段过载，则将任务分配给另一个未重载的处理器或线程。

3. 发明授权

US5742536A Parallel calculation of exponent and sticky bit during normalization 失效
标题翻译：在归一化期间并行计算指数和粘点
公开(公告)号：US5742536A
公开(公告)日：1998-04-21
申请号：US478416
申请日：1995-06-07
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional damflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.
摘要翻译：根据分数位移数据流，根据将指数分解成部分指数组，实现用于在归一化期间确定分数移位的方法来确定指数的方法，根据分数确定每个部分指数组的所有可能的部分指数值数据流，并且通过根据分数据流选择性地组合来自每个部分指数组的可能部分指数来提供指数。还提供了一种实现在归一化过程中产生粘性位的方法的系统。粘滞位信息根据分数据流进行预先计算和复用。在本发明的一个实施例中，以树形式计算组粘性信号，每组粘性具有与多路复用的移位增量量相对应的多个可能的粘性位。组粘性位根据分数阻力流中的后续移位量进一步复用，以在与最终分数位移量可用时基本相同的时间提供输出粘性位，从而与标准化分数基本上相同。

4. 发明授权

US5742535A Parallel calculation of exponent and sticky bit during normalization 失效
公开(公告)号：US5742535A
公开(公告)日：1998-04-21
申请号：US461676
申请日：1995-06-05
申请人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
发明人： Eric Mark Schwarz , Robert Michael Bunce , Leon Jacob Sigal , Hung Cai Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional dataflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.

5. 发明授权

US5654911A Carry select and input select adder for late arriving data 失效
公开(公告)号：US5654911A
公开(公告)日：1997-08-05
申请号：US472962
申请日：1995-06-07
申请人： Eric Mark Schwarz , Robert Michael Bunce
发明人： Eric Mark Schwarz , Robert Michael Bunce
IPC分类号： G06F7/50 , G06F7/507
CPC分类号： G06F7/507
摘要： An adder which takes advantage of the early arriving bits of a time skewed operand to provide a result to an add or substract operation without additional latency. Possible partial results are calculated and then selectively combined according to the late arriving data as the late arriving data becomes available. In an embodiment of the present invention, a first operand is partitioned into groups according to the arrival time of the skewed data, and possible partial results for each group are calculated for the full range of partial inputs that affect it. In addition, the high order groups are calculated with and without a borrow (carry) which is propagated from a low order group. Once the delayed partial operands are known and the borrows (carrys) determined the partial results are gated through multiplexers according to the borrows and partial results, and thus the result is provided with a delay similar to the delay in arrival of the skewed operand.

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